Intermediate-Node DCD Sampling in Low-Swing Transmitters
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Solution Overview
Problem
Conventional chip-to-chip (C2C) SERDES interfaces face challenges with duty cycle distortion (DCD) due to the asymmetric rise and fall times of low-swing output signals, which limits the baud rate and introduces complexity in duty cycle correction (DCC).
Innovation Solution
The proposed solution involves a low-swing transmitter with a high-swing output driver and a passive continuous-time linear equalization (CTLE) circuit, which allows for DCD sampling and correction at an intermediate node before the attenuator, eliminating the need for additional hardware and reducing system complexity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If conventional N-over-N output driver is used to generate low swing transmit signal, then low power consumption is achieved, but additional low voltage supply is required which reduces interface throughput
Solution Approach 1:
The patent combines the low voltage supply function with existing power supply bumps by utilizing the same bumps that provide high voltage supply, thereby eliminating the need for separate low voltage supply bumps and maintaining full interface throughput while achieving low power consumption through low swing signaling
2Use of energy by moving object
If conventional N-over-N output driver is used, then low swing output signal is generated, but rise and fall times are inherently different causing duty cycle distortion
Solution Approach 1:
The patent introduces an intermediary measurement point at the output of the CMOS amplifier stage, before the signal passes through the attenuator. This allows duty cycle distortion measurement at a point where the signal characteristics are more favorable for accurate measurement, enabling proper duty cycle correction without affecting the low power benefit of low swing signaling
3Manufacturing precision
If duty cycle correction is implemented using conventional methods, then DCD estimation is achieved, but additional hardware is required that affects measured DCD and increases system complexity
Solution Approach 1:
The patent extracts the duty cycle measurement function from the signal path by using an intermediate measurement point that does not require additional hardware components in the main signal path. This allows duty cycle correction to be implemented using existing circuitry, reducing system complexity while maintaining measurement accuracy
4Manufacturing precision
If additional asynchronous sampling is used for DCC, then duty cycle correction is achieved, but system complexity increases due to clock swapping and loopback requirements
Solution Approach 1:
The patent enables the system to perform duty cycle measurement and correction using its existing clocking infrastructure and signal paths. By measuring duty cycle at an intermediate point and using the same clock domain, the system corrects its own duty cycle distortion without requiring external asynchronous sampling or loopback mechanisms, thereby maintaining low system complexity
Data Source
AI summary
Technologies for duty cycle distortion (DCD) estimation are described. A transmitter includes a first output driver comprising a first complementary metal-oxide semiconductor (CMOS) amplifier and a first attenuator coupled to an output of the first CMOS amplifier. The first CMOS amplifier receives an input signal and outputs an intermediate signal to the first attenuator. The first attenuator receives the intermediate signal and outputs an output signal having a signal swing that is less than a signal swing of the input signal. A first duty cycle correction (DCC) loop is coupled to the first output driver. The first DCC loop estimates first DCD in the intermediate signal output by the first CMOS amplifier.