Internal Voltage Generating Circuit Dynamic Frequency Control
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Solution Overview
Problem
Conventional internal voltage generating circuits face inefficiencies in reducing setup time for the second charge pump circuit while increasing the number of circuits and area, requiring additional smoothing capacitance to prevent ripple at the second output node.
Innovation Solution
Incorporating a frequency dividing circuit to divide the clock signal and a buffer circuit to select and supply the clock signals to the second charge pump circuit, allowing the boosted voltage from the first charge pump circuit to be used as input for the second charge pump circuit with low current supply capability, and controlling the charge pump circuits with high voltage detecting circuits to reduce setup time and stabilize output.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If the number of circuits is increased to reduce setup time for the second charge pump circuit, then the setup time is reduced, but the circuit area increases
Solution Approach 1:
The patent dynamically switches between two clock signal frequencies supplied to the second charge pump circuit. During the initial phase, a higher frequency clock signal is supplied to reduce setup time. After the boosted voltage reaches a predetermined level, the frequency is reduced. This dynamic frequency switching allows the circuit to achieve fast setup without requiring additional parallel circuits, thereby reducing circuit area while maintaining fast setup time.
2Stability of the object's composition
If additional smoothing capacitance is added to prevent ripple at the second output node, then output voltage stability is improved, but circuit area and complexity increase
Solution Approach 1:
The patent employs periodic action by switching the clock signal frequency in two distinct phases. In the first phase, a higher frequency operates the second charge pump circuit to quickly establish the boosted voltage. In the second phase, after the voltage reaches the target level, the frequency is reduced to minimize ripple. This periodic frequency modulation inherently suppresses output voltage ripple without requiring additional smoothing capacitance, thus avoiding increased circuit complexity.
3Speed
If the clock signal frequency is increased to reduce setup time, then charging speed is improved, but output voltage fluctuation increases
Solution Approach 1:
The patent dynamically adjusts the clock signal frequency based on the charging state. During the initial charging phase, a higher frequency is applied to achieve fast charging speed. Once the boosted voltage reaches a predetermined level, the frequency is automatically reduced. This dynamic frequency adjustment ensures that high charging speed is achieved only when necessary, while output voltage stability is maintained during the steady-state operation, effectively resolving the contradiction between speed and stability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach reduces the setup time of the second charge pump circuit, concentrates current supply to the output load of the first charge pump circuit, and provides a more stable boosted voltage and current supply, while preventing fluctuations in output voltage.
Implementation Method 1
a first charge pump circuit configured to generate a second voltage from a first voltage, a second charge pump circuit configured to generate a third voltage from the second voltage
Implementation Method 2
a frequency dividing circuit configured to divide a first clock signal to be supplied to the first boost circuit to generate a second clock signal
Data Source
AI summary
An output terminal of a first boost circuit is connected to a second boost circuit. After the second boost circuit is started up, a boost clock frequency of the second boost circuit is reduced. A time required to start up the second boost circuit is reduced, and in addition, a current supply capability of the first boost circuit is increased after the second boost circuit is started up. When the second boost circuit is driven, output voltages of the first and second boost circuits are stably supplied without instantaneously changing the output voltage of the first boost circuit.