Interpolated Delay-Line TDC Circuit for Finer Time Resolution
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Solution Overview
Problem
Current time to digital converters face limitations in resolution due to minimum stage delay constraints in inverter circuits, which restrict the precision of time-based signal conversion.
Innovation Solution
The implementation of a time delay circuit with dual delay lines and interpolation circuits that generate intermediate signals through analogue interpolation, allowing for increased resolution by synchronizing and inverting signals, and using passive voltage dividers or differential amplifiers to enhance time measurement precision.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If inverter circuits are used for time delay, then device simplicity is maintained, but resolution is limited by minimum stage delay constraints
Solution Approach 1:
The patent divides the time delay function into multiple identical delay stages connected in series. Each stage provides a fixed delay time, and by cascading multiple stages, the total delay can be precisely controlled. This segmentation allows achieving high resolution time measurement without requiring complex individual delay elements.
Solution Approach 2:
The patent introduces D-type flip-flops as intermediary elements between delay stages. These flip-flops sample and hold the signal at specific time points, enabling precise time measurement by capturing the state of delayed signals at defined moments. This intermediary mechanism resolves the limitation of direct inverter delay measurement.
2Measurement precision
If more delay stages are added to increase resolution, then measurement precision improves, but device complexity and fabrication variation sensitivity increase
Solution Approach 1:
The patent changes the delay parameter from continuous inverter propagation delay to discrete flip-flop clocked sampling. By using the clock edge of the flip-flop as the reference timing point rather than relying on continuous signal propagation through multiple inverters, the measurement becomes less sensitive to fabrication variations in transistor dimensions and material properties.
Solution Approach 2:
The patent employs feedback through the clock signal that drives all flip-flops simultaneously. This common clock reference ensures that all delay stages are sampled at the same time point, providing a unified reference frame that compensates for individual stage variations and improves overall measurement reliability.
3Measurement precision
If dual delay lines with interpolation circuits are implemented, then resolution is significantly enhanced, but device complexity increases
Solution Approach 1:
The patent transitions from a single delay line to dual delay lines operating in parallel. One delay line processes the original signal while the other processes an inverted version. This dimensional expansion allows interpolation between the two delay paths, effectively doubling the measurement resolution without requiring four times the number of delay stages in a single line.
Solution Approach 2:
The patent introduces asymmetry by using one inverted signal path alongside the non-inverted path. This asymmetric configuration enables the interpolation circuit to detect half-cycle delays, effectively achieving 2N resolution from N physical stages. The asymmetric inversion breaks the symmetry limitation of conventional delay measurement.
Data Source
AI summary
A time delay circuit is disclosed and includes a delay line with a first delay circuit and at least a second delay circuit connected downstream. An interpolation circuit is used to generate intermediate signals derived by delayed successive signals in the delay line.