Interpolation Circuit With Dual-ADC Quantization for Asynchronous Reception
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Solution Overview
Problem
High data rate signal transmission/reception in communication devices leads to increased quantization bits in ADCs, which can reduce receiving sensitivity and result in larger circuit sizes, particularly in asynchronous reception circuits where sampling is out of synchronization with the input data phase.
Innovation Solution
An interpolation circuit is designed with a generation circuit to produce interpolated data, utilizing a first ADC with a higher number of quantization bits at data points and a second ADC with fewer quantization bits at change points, along with a selection circuit to determine the appropriate ADC for each data point or change point based on phase differences, thereby optimizing ADC usage and reducing circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If the number of quantization bits in ADC is increased to maintain receiving sensitivity at high data rates, then measurement precision is improved, but device complexity and circuit size increase
Solution Approach 1:
The patent segments the ADC operation into two distinct modes: a first ADC with higher quantization bits for data points, and a second ADC with fewer quantization bits for change points. This segmentation allows the system to use high precision only where necessary (data points) while using lower precision where it suffices (change points), thereby reducing overall circuit complexity while maintaining receiving sensitivity.
Solution Approach 2:
The patent applies local quality by assigning different quantization bit depths to different operational contexts. Data points receive higher quantization precision (first ADC) while change points use lower precision (second ADC). This localized differentiation optimizes the balance between measurement precision and device complexity by matching precision requirements to specific functional needs.
2Adaptability or versatility
If sampling is performed out of synchronization with input data phase in asynchronous reception, then adaptability is improved, but measurement precision deteriorates due to quantization errors
Solution Approach 1:
The patent implements dynamic adaptation by using a selection circuit that determines whether to use the first ADC or second ADC based on real-time detection of change points. This dynamic switching allows the system to adapt to varying signal conditions in asynchronous reception, maintaining measurement precision by using higher precision conversion when change points are detected, while preserving asynchronous reception capability through flexible mode switching.
Solution Approach 2:
The patent employs feedback through a change point detection mechanism that monitors the input signal and provides control signals to the selection circuit. This feedback loop enables the system to automatically adjust between the first and second ADC based on detected signal characteristics, thereby maintaining measurement precision while supporting asynchronous reception operations.
3Measurement precision
If a single ADC with high quantization bits is used for all data points, then measurement precision is maintained, but device complexity increases
Solution Approach 1:
The patent segments the ADC functionality into two separate ADC units with different quantization bit depths. The first ADC handles data points with higher precision, while the second ADC handles change points with lower precision. This segmentation reduces overall device complexity compared to using a single high-precision ADC for all operations, while maintaining necessary measurement precision for critical data points.
Solution Approach 2:
The patent applies partial action by using high quantization precision (first ADC) only for data points where it is necessary, rather than applying it universally. For change points, lower precision (second ADC) suffices. This partial application of high precision reduces device complexity while maintaining adequate measurement precision for the specific requirements of each operation type.
Data Source
AI summary
An interpolation circuit includes: a generation circuit configured to generate interpolated data based on a plurality of pieces of input data in time sequence; a first analog digital converter configured to convert first interpolated data at a data point of the interpolated data into first digital data; and a second analog digital converter configured to convert second interpolated data at a change point into second digital data of the interpolated data, a second number of quantization bits of the second analog digital converter being smaller than a first number of quantization bits of the first analog digital converter.