Interpolative Divider VCXO for Multi-Output Clock Control
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Solution Overview
Problem
Existing solutions for voltage-controlled oscillators (VCXOs) face challenges in cost, size, and reliability due to the need for multiple crystal oscillators and phase-locked loops (PLLs) with LC oscillators, which result in increased silicon area and power consumption, as well as signal crosstalk issues when multiple oscillators operate at close frequencies.
Innovation Solution
The use of a reference clock generator and interpolative dividers, coupled with phase interpolators and delta sigma modulators, allows for the generation of multiple independent output frequencies using a single PLL, reducing the need for multiple PLLs and minimizing silicon area while eliminating crosstalk by using a single reference clock signal and arithmetic combination of divide ratios with digital voltage control signals.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If multiple crystal oscillators are used to provide multiple VCXOs, then multiple independent frequency outputs are achieved, but cost, size, and reliability deteriorate
Solution Approach 1:
The patent merges multiple VCXO functions into a single integrated circuit that uses one crystal oscillator and multiple interpolative dividers. This consolidation eliminates the need for multiple separate crystal oscillators, thereby improving reliability while maintaining the capability to provide multiple independent frequency outputs through digital control of the interpolative dividers.
Solution Approach 2:
The single VCXO circuit is designed to perform multiple functions by generating multiple frequency outputs through interpolative dividers. The circuit can be configured to provide different frequency outputs simultaneously or independently, making it a universal solution that replaces multiple dedicated oscillators.
2Adaptability or versatility
If multiple PLLs with LC oscillators are used to provide VCXO functionality, then frequency control flexibility is improved, but silicon area and power consumption increase
Solution Approach 1:
The patent combines the functionality of multiple PLLs with LC oscillators into a single VCXO circuit that uses one crystal oscillator and multiple interpolative dividers. This merging dramatically reduces silicon area while maintaining frequency control flexibility through digital manipulation of the interpolative dividers.
Solution Approach 2:
The patent replaces the mechanical/LC oscillator-based frequency generation with a digital approach using interpolative dividers. By substituting the LC resonance mechanism with digital frequency division and interpolation, the circuit achieves comparable frequency control flexibility with significantly reduced silicon area and power consumption.
3Adaptability or versatility
If multiple LC oscillators with close frequencies are placed on the same die, then multiple frequency outputs are achieved, but signal crosstalk increases
Solution Approach 1:
The patent merges multiple frequency generation functions into a single oscillator circuit with multiple interpolative dividers. This eliminates the need for multiple LC oscillators operating at close frequencies, thereby removing the source of signal crosstalk while still providing multiple frequency outputs through digital control.
4Adaptability or versatility
If multiple crystal oscillators are used to provide multiple VCXOs, then multiple independent frequency outputs are achieved, but device complexity increases
Solution Approach 1:
The patent merges multiple VCXO circuits into a single integrated structure that shares a common crystal oscillator and uses interpolative dividers for frequency multiplication. This consolidation reduces device complexity by eliminating redundant oscillator circuits while maintaining the capability to provide multiple independent frequency outputs through digital control of the dividers.
Data Source
AI summary
An oscillator output is controlled from an external voltage control terminal using an interpolative divider as a frequency modulator. The oscillator includes a reference clock generator, analog to digital converter, and an interpolative divider. Nominal output frequency is determined by the frequency of the reference clock and the nominal divide value of the interpolative divider. The divide value is changed according to the voltage control input value which is converted to a digital value via an analog to digital converter. Multiple interpolative dividers may be coupled to the single reference clock generator and each have a voltage control input and analog to digital converter.


