Interposer Package Layout With 3D Stacking and Redistribution Routing
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Solution Overview
Problem
Existing semiconductor packages face challenges in reducing the size of interposer substrates while ensuring reliable connection and increased connection terminals for input/output, which affects the compactness and functionality of electronic devices.
Innovation Solution
A semiconductor package design incorporating an interposer with a reduced size, featuring a chip through via, redistribution layers, and molding layers to connect semiconductor chips efficiently, reducing signal distance and improving connection reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If the interposer substrate size is reduced, then the compactness and signal distance are improved, but the connection reliability and manufacturing yield deteriorate
Solution Approach 1:
The interposer substrate is segmented into multiple regions with different functional layers (lower molding layer, redistribution layer, upper molding layer) that can be independently optimized. This segmentation allows the substrate to maintain reduced overall size while ensuring reliable connections through specialized zones for signal transmission and structural support.
Solution Approach 2:
The patent transitions from a conventional two-dimensional interposer layout to a three-dimensional stacked architecture with lower and upper semiconductor chips positioned at different vertical levels. This dimensional change enables shorter signal paths and improved connection reliability within a compact volume, as signals travel vertically through chip through vias rather than horizontally across a large substrate.
2Length of moving object
If the interposer substrate size is reduced, then the signal distance between chips is reduced, but the process yield deteriorates
Solution Approach 1:
The lower molding layer is formed to cover the lower semiconductor chip and extend onto the interposer substrate before the redistribution layer is deposited. This preliminary action creates a pre-defined structure that guides subsequent processing steps, ensuring proper alignment and reducing manufacturing variability, thereby improving process yield despite the reduced substrate size.
Solution Approach 2:
The structure employs nested layers where the lower molding layer is nested within the interposer substrate, the redistribution layer is nested on top of the molding layer, and the upper molding layer is nested around the upper semiconductor chip. This nested architecture maximizes the use of available space in the reduced substrate while maintaining all necessary functional layers for high-yield manufacturing.
3Quantity of substance
If more connection terminals are added, then the I/O capacity is increased, but the device complexity increases
Solution Approach 1:
The redistribution layer acts as an intermediary between the lower and upper semiconductor chips, providing a complex routing network that enables multiple connection terminals without requiring direct complex interconnections between chips. This intermediary layer simplifies the overall package structure by centralizing the interconnection logic in a dedicated redistribution network.
Solution Approach 2:
The patent utilizes the vertical dimension to stack multiple semiconductor chips and connection terminals at different height levels. This three-dimensional arrangement allows a high density of connection terminals to be achieved without proportionally increasing the horizontal footprint or planar complexity, as terminals are distributed across multiple vertical layers rather than all residing in a single plane.
Data Source
AI summary
A semiconductor package includes an interposer, a lower semiconductor chip located on the interposer and including a chip through via, lower stack structures located on the interposer and spaced apart from the lower semiconductor chip in a horizontal direction, a lower molding layer located on the interposer, a redistribution layer located on the lower molding layer, the lower semiconductor chip, and the lower stack structures and electrically connected to the chip through via of the lower semiconductor chip, an upper semiconductor chip located on the redistribution layer and electrically connected to the redistribution layer, upper stack structures spaced apart from the upper semiconductor chip in the horizontal direction, located on the redistribution layer, and electrically connected to the redistribution layer, and an upper molding layer located on the redistribution layer and on side surfaces of the upper semiconductor chip and side surfaces of each of the upper stack structures.