Interposer With Active And Passive Pads For Semiconductor Chip Inspection
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Solution Overview
Problem
Manufacturing a package to inspect the reliability of high-performance semiconductor chips, such as Wide IO2, is challenging due to the large number of bumps and micro bumps, making it difficult to use conventional methods like wire bonding for effective inspection.
Innovation Solution
An interposer with a new pad structure is introduced, featuring active and passive pads on one surface and bump pads on the opposite surface, allowing for both active and passive mode inspections, enabling data input/output, control signals, and power supply for reliable testing of high-performance semiconductor chips.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If conventional wire bonding method is used for manufacturing inspection package, then manufacturing process is simple, but it is difficult to inspect reliability of micro bumps on high-performance semiconductor chips
Solution Approach 1:
The patent introduces an interposer as an intermediary component between the semiconductor chip and the substrate. The interposer includes a first surface with active pads and passive pads, and a second surface with bump pads that couple to the chip's bumps. This intermediary structure enables reliable inspection of micro bumps through controlled electrical connections, solving the measurement precision problem while maintaining manufacturing feasibility through standardized pad configurations.
2Reliability
If package is manufactured using only the high-performance semiconductor chip, then inspection is straightforward, but it is nearly impossible to manufacture package for inspecting chips with large number of bumps
Solution Approach 1:
The patent segments the inspection package into distinct functional components: the semiconductor chip, the interposer with separated active and passive regions, and the substrate. The interposer itself is segmented into active pads for data/control signals, passive pads for power supply, and bump pads for chip coupling. This segmentation allows each component to be optimized independently, improving inspection reliability while managing device complexity through modular design.
Solution Approach 2:
The patent transitions from a direct two-dimensional chip-to-substrate connection to a three-dimensional structure incorporating the interposer as an intermediate layer. The interposer adds a vertical dimension with multiple surfaces (first surface with pads, second surface with bump pads), enabling complex electrical connections to be distributed across multiple layers and regions, thereby improving inspection reliability for chips with large numbers of bumps.
3Adaptability or versatility
If active mode testing is implemented, then data and control signals can be transmitted, but additional pads and power supply circuits are required
Solution Approach 1:
The patent designs the interposer with multi-functional pads that can serve different purposes. The active pads on the first surface can handle both data transmission and control signals, while also providing power supply connections. The passive pads are dedicated to power supply functions. This universal design allows the interposer to support both active mode testing (with data和控制 signals) and passive mode testing (with power supply only), providing testing mode flexibility without requiring completely separate pad structures for each mode.
Data Source
AI summary
An interposer for inspecting reliability of a semiconductor chip is disclosed. The interposer for inspection includes: at least one active pad disposed in an active region of a first surface, and including: pads through which data and a control signal for testing an inspection target chip are received (input) and sent (output) during an active mode; and pads for receiving a power-supply voltage needed to operate the inspection target chip and the interposer during the active mode; at least one passive pad disposed in a passive region of the first surface, and including: pads receiving data for testing the inspection target chip during a passive mode, and a power-supply voltage needed to operate the inspection target chip and the interposer during the passive mode; and at least one bump pad disposed over a second surface facing the first surface, and to be coupled to the inspection target chip.