Interposer Board Without Feature Layer for High Density IO
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Solution Overview
Problem
The miniaturization of interposer boards is limited by the minimum spacing between feature layers, which restricts the increase in IO number due to apparatus resolution limits, leading to larger product sizes and parasitic capacitance issues that cause heat generation and signal loss.
Innovation Solution
A method for manufacturing an interposer board without a feature layer structure, involving a temporary carrier with Cu foils, lamination of insulating materials, forming vias, filling with metal, and removing the edge seal and carrier, resulting in an insulating layer with embedded Cu via-posts that can be closer together, breaking the apparatus resolution limit and reducing parasitic effects.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a feature layer structure is used in the interposer board, then the pads can be formed for wire bonding and solder balls, but the minimum spacing between features restricts further miniaturization and increases product size
Solution Approach 1:
The patent extracts and removes the feature layer from the traditional three-layer interposer board structure, retaining only the essential via-posts and insulating layer. This extraction eliminates the pads and alignment annular rings that consume space, allowing via-posts to serve directly as connection points without requiring additional feature layer structures.
Solution Approach 2:
The patent merges the function of the feature layer pads with the via-posts themselves. Instead of having separate via-posts and pads, the via-post ends directly serve as the connection terminals, combining multiple functions into a single structural element and eliminating the need for additional spacing.
2Manufacturing precision
If the feature layer is present with alignment annular ring, then alignment between via-post and feature layer can be achieved, but parasitic capacitance increases causing heat generation and signal loss
Solution Approach 1:
The patent removes the alignment annular ring structure from the feature layer, eliminating the source of parasitic capacitance. The via-posts are formed directly on the insulating layer without requiring an intermediate feature layer with alignment rings, thus extracting the harmful capacitive effect while maintaining electrical connection functionality.
Solution Approach 2:
The patent converts the alignment requirement from a geometric constraint into a direct electrical connection advantage. By eliminating the feature layer, the via-post ends become the direct connection points, transforming what was previously a multi-layer alignment challenge into a simplified single-layer structure that inherently reduces parasitic effects.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach allows for a significant increase in IO channels per unit area, saving space and reducing parasitic effects, thereby enhancing integration density and product performance by eliminating the feature layer and using Cu via-posts as interposing IO channels.
Implementation Method 1
laminating an insulating material onto upper and lower surfaces of the temporary carrier to form an insulating layer
Implementation Method 2
filling the via with a metal
Implementation Method 3
filling the via by a manner of electroplating or chemical plating
Data Source
AI summary
A method for manufacturing an interposer board without a feature layer structure according to an embodiment of the present invention may include preparing a temporary carrier; forming an edge seal for the temporary carrier; laminating an insulating material onto upper and lower surfaces of the temporary carrier to form an insulating layer; forming a via on the insulating layer, filling the via with a metal; and removing the edge seal and removing the temporary carrier. An interposer board without a feature layer structure according to an embodiment of the present invention may include an insulating layer and a via-post layer embedded in the insulating layer, wherein the via-post has an end used as a pad.