Interposer Boundary-Scan Circuit for Stacked Die Testing
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Solution Overview
Problem
The IEEE 1149.1 standard for boundary scan testing in integrated circuits (ICs) is not widely used in memory and analog ICs due to increased package size and decreased input/output performance, and existing access methods for stacked die configurations require multiple TMS signals, non-compliance with IEEE standards, and prolonged test times.
Innovation Solution
An interposer is enhanced to include IEEE 1149.1 TAP circuitry, allowing for serial access of multiple TAPs with a single TMS signal and eliminating the need for individual selection of TAPs, while optimizing test data transfer through boundary registers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If IEEE 1149.1 boundary scan circuitry is included in integrated circuits, then boundary scan testing capability is improved, but package size increases and input/output performance decreases
Solution Approach 1:
The patent divides the boundary scan testing function into separate modules: the interposer contains TAP circuitry and boundary scan cells, while the ICs contain only the functional circuits. This segmentation allows the testing capability to be distributed across multiple components rather than embedded in each IC, achieving testing functionality without increasing individual IC package sizes.
Solution Approach 2:
The interposer acts as an intermediary component between the substrate and the ICs, providing the IEEE 1149.1 TAP interface and boundary scan functionality. This mediator approach allows standard-compliant testing without modifying the ICs themselves, thus avoiding the package size and performance penalties associated with integrating TAP circuitry directly into each IC.
2Reliability
If multiple TAPs in stacked die configurations are accessed using existing methods, then test coverage is improved, but test time increases and IEEE standard compliance is lost
Solution Approach 1:
The patent merges multiple TAP control functions into a single unified TAP interface on the interposer. The interposer's TAP circuitry can simultaneously control and access multiple TAPs in the stacked die configuration through a single TMS signal, eliminating the need for multiple separate TMS signals and reducing test time while maintaining IEEE 1149.1 compliance.
Solution Approach 2:
The interposer's TAP interface is designed with universal functionality to access multiple different TAPs across stacked die configurations. A single TAP interface can selectively control any TAP in the stack through appropriate signal routing and control logic, providing multi-functional access that reduces test time and maintains standard compliance.
3Measurement precision
If individual selection of TAPs is required in stacked die configurations, then test precision is improved, but device complexity increases
Solution Approach 1:
The interposer's TAP interface automatically handles the complexity of selecting and accessing individual TAPs in the stacked die configuration. The control logic within the interposer self-manages the signal routing and TAP selection based on the test requirements, eliminating the need for external complex selection mechanisms and reducing overall system complexity while maintaining precise TAP access.
Data Source
AI summary
The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.