Interposer Buffer Layout for High-Density Package Integration
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Solution Overview
Problem
The increasing miniaturization of semiconductor chips and the need for higher I/O pad density in packaging pose challenges, leading to difficulties in yield and limitations in conventional packaging technologies, such as solder bridges and reduced I/O pad numbers due to pitch constraints.
Innovation Solution
The integration of a System on Integrate Chip (SoIC) package bonded to an Integrated Fan-Out (InFO) package, utilizing interposer wafers without organic dielectric materials, hybrid bonding, and inorganic gap-filling and redistribution layers to enhance routing and reduce warpage, allowing for fine-pitch metal lines and high-density bond pads.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the pitch of the I/O pads is decreased to increase density, then the number of I/O pads per area increases, but solder bridges occur between adjacent pads
Solution Approach 1:
The patent introduces an interposer wafer as an intermediary substrate between the device die and the package substrate. This interposer wafer provides a larger area for redistributing I/O pads, allowing the pads to be spaced farther apart on the package substrate while maintaining high connectivity density. The interposer acts as a mediator that decouples the conflicting requirements of high pad density and sufficient pad spacing to prevent solder bridges.
Solution Approach 2:
The patent transitions from a two-dimensional planar arrangement of I/O pads directly on the device die to a three-dimensional stacked architecture using an interposer wafer. This vertical integration allows I/O pads to be redistributed across multiple layers and a larger footprint area, effectively increasing the usable packing area without decreasing the pitch on the original die surface.
2Ease of manufacture
If organic dielectric materials are used in the interposer wafer, then the manufacturing process is simpler, but warpage occurs due to thermal expansion mismatch
Solution Approach 1:
The patent changes the material parameter of the interposer wafer from organic dielectric materials to inorganic materials. This material substitution fundamentally alters the thermal expansion characteristics, enabling the interposer to have a thermal expansion coefficient that better matches the device die and package substrate, thereby reducing warpage while maintaining manufacturability through established inorganic material processing techniques.
3Productivity
If fan-in packaging is used with small dies, then throughput is higher and cost is lower, but the number of I/O pads is limited by die area
Solution Approach 1:
The patent employs a fan-out packaging approach using an interposer wafer that redistributes I/O pads to a larger area than the original die footprint. This dimensional expansion allows significantly more I/O pads to be accommodated while maintaining the high throughput of wafer-level processing, as multiple dies can still be processed simultaneously on the wafer before dicing.
Solution Approach 2:
The patent segments the packaging process into distinct stages: wafer-level die attachment to the interposer, followed by dicing to separate individual packages. This segmentation allows the benefits of wafer-level processing (high throughput) to be combined with the benefits of fan-out packaging (high I/O density), as the redistribution to larger area occurs at the wafer level before final package separation.
4Quantity of substance
If fan-out packaging is used to increase I/O pad density, then more I/O pads can be packed, but the packaging process becomes more complex
Solution Approach 1:
The patent performs the complex redistribution of I/O pads in advance during the wafer-level processing stage, before the packages are diced and assembled. The interposer wafer is prepared with the complete pad redistribution pattern beforehand, and multiple dies are attached to it in a single wafer-level process. This preliminary action consolidates the complexity into one stage rather than requiring complex operations during final package assembly.
Data Source
AI summary
A method of forming a package includes bonding a device die to an interposer wafer, with the interposer wafer including metal lines and vias, forming a dielectric region to encircle the device die, and forming a through-via to penetrate through the dielectric region. The through-via is electrically connected to the device die through the metal lines and the vias in the interposer wafer. The method further includes forming a polymer layer over the dielectric region, and forming an electrical connector. The electrical connector is electrically coupled to the through-via through a conductive feature in the polymer layer. The interposer wafer is sawed to separate the package from other packages.