Interposer Frame Vertical Interconnects for Semiconductor Packaging
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Solution Overview
Problem
Conventional fan-out wafer level chip scale package (Fo-WLCSP) manufacturing is hindered by complex and costly processes for forming conductive pillars and redistribution layers (RDLs) for z-direction vertical electrical interconnects.
Innovation Solution
The use of a pre-formed interposer frame with conductive pillars over a semiconductor die, where an encapsulant is deposited and an interconnect structure is formed to electrically connect with the pillars, simplifying the assembly process and reducing the need for RDL patterning and conductive pillar formation through the encapsulant.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional processes are used to form conductive pillars and redistribution layers for z-direction vertical electrical interconnects, then reliable electrical connection is achieved, but manufacturing complexity and cost increase significantly
Solution Approach 1:
Conductive pillars are formed on the interposer substrate before the semiconductor die is mounted. This preliminary formation of conductive structures eliminates the need for complex subsequent lithography, etching, and metal deposition processes that would otherwise be required to create redistribution layers and vertical interconnects after die attachment, thereby reducing manufacturing complexity while maintaining connection reliability
Solution Approach 2:
An interposer substrate is introduced as an intermediary component between the semiconductor die and the final package substrate. This interposer carries pre-formed conductive pillars that provide vertical electrical interconnects, simplifying the overall manufacturing process by decoupling the complex interconnect formation from the die attachment process and enabling more straightforward routing of electrical signals
2Reliability
If conventional RDL patterning and conductive pillar formation through encapsulant are used, then vertical electrical interconnect is achieved, but manufacturing time and cost increase
Solution Approach 1:
The conductive pillars are formed on the interposer substrate before die mounting and encapsulation, rather than forming them through the encapsulant material after assembly. This resequencing of manufacturing steps eliminates time-consuming lithography and etching operations that would otherwise be required to create vias through the encapsulant, thereby improving manufacturing efficiency while ensuring reliable vertical electrical interconnects
Solution Approach 2:
The manufacturing process is segmented into distinct stages: interposer preparation with conductive pillar formation, die mounting, encapsulation, and final interconnect formation. This segmentation allows each stage to be optimized independently and enables parallel processing of multiple devices, improving overall manufacturing throughput while maintaining interconnect reliability
Data Source
AI summary
A semiconductor device has a first semiconductor die mounted over a carrier. An interposer frame has an opening in the interposer frame and a plurality of conductive pillars formed over the interposer frame. The interposer is mounted over the carrier and first die with the conductive pillars disposed around the die. A cavity can be formed in the interposer frame to contain a portion of the first die. An encapsulant is deposited through the opening in the interposer frame over the carrier and first die. Alternatively, the encapsulant is deposited over the carrier and first die and the interposer frame is pressed against the encapsulant. Excess encapsulant exits through the opening in the interposer frame. The carrier is removed. An interconnect structure is formed over the encapsulant and first die. A second semiconductor die can be mounted over the first die or over the interposer frame.