Interposer Frame Polymer Matrix Via Fabrication
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current drill & fill technology for fabricating interconnects in IC substrates and interposers is limited by low throughput, high costs, and difficulties in creating high-density, varied via sizes and shapes, leading to reliability issues and electrical challenges due to rough side walls and tapering, which restricts miniaturization and increases manufacturing costs.
Innovation Solution
The use of pattern plating or panel plating technologies to deposit copper via posts in a dielectric matrix, allowing for the creation of high-density, varied via geometries and shapes, with the option of using a polymer matrix reinforced with glass fibers, enabling the fabrication of coreless laminar structures and reducing warping, thereby improving planarity and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If laser drilling is used to create vias through dielectric substrate, then via creation is achieved, but throughput rate is limited and manufacturing cost increases
Solution Approach 1:
The patent replaces the mechanical laser drilling process with an electrochemical etching process. Instead of using a laser to physically remove material, the invention uses electrochemical reactions to selectively remove dielectric material and form vias. This substitution enables parallel processing of multiple vias simultaneously, dramatically increasing throughput rate while reducing manufacturing cost per via.
Solution Approach 2:
The patent changes the fundamental parameter of via creation from thermal/mechanical (laser) to electrochemical. By controlling electrochemical etching parameters such as current density, etchant composition, and exposure time, the process achieves high-speed via formation. This parameter change enables simultaneous creation of numerous vias with different geometries in parallel, resolving the throughput limitation of sequential laser drilling.
2Manufacturing precision
If laser drilling is used to create vias, then via holes are formed, but side walls become rough and taper inwards reducing effective diameter
Solution Approach 1:
The patent replaces laser drilling with electrochemical etching, which fundamentally changes how via holes are formed. The electrochemical process removes material through controlled chemical reactions rather than thermal ablation, producing smooth, vertical side walls without the inward tapering characteristic of laser-drilled holes. This substitution directly improves both via geometry control and electrical contact reliability.
Solution Approach 2:
The patent changes the physical-chemical mechanism from thermal/photomechanical (laser) to electrochemical. By controlling electrochemical parameters such as current distribution, etchant concentration, and exposure time, the process achieves precise control over via diameter and side wall morphology. This parameter control ensures uniform, non-tapering via geometries that maintain reliable electrical contacts, directly addressing the reliability issues caused by laser drilling.
3Adaptability or versatility
If drill & fill methodology is used, then vias are created, but high density of varied via sizes and shapes is difficult to produce
Solution Approach 1:
The patent changes the via creation process from mechanical drilling to electrochemical etching, enabling simultaneous fabrication of high-density via arrays with varied geometries. By controlling electrochemical parameters (current density, exposure time, etchant composition), the process can create different via sizes and shapes in parallel, achieving both high productivity and geometric versatility that are mutually exclusive in traditional drill & fill methods.
Solution Approach 2:
The patent employs preliminary patterning steps where photoresist or other masking materials are applied before electrochemical etching. This preliminary action defines the precise locations and geometries of vias before the etching process begins, enabling complex via arrays with varied sizes and shapes to be created in a single parallel process, thereby achieving high density and versatility simultaneously.
4Ease of manufacture
If electroplating is used to fill drilled via holes, then via filling is achieved, but dimpling and overfill occur creating stacking difficulties
Solution Approach 1:
The patent replaces the electroplating filling process with a different approach. Instead of depositing metal through electroplating into drilled holes, the invention uses electrochemical etching to create precisely defined via channels that can be directly filled or formed without the dimpling and overfill problems of electroplating. This substitution eliminates the root cause of stacking difficulties while maintaining ease of manufacture.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the production of high-density interconnects with smaller via diameters and varied geometries, reducing manufacturing costs and improving reliability, while allowing for the creation of thinner, more powerful electronic components with enhanced electrical performance.
Implementation Method 1
The filling process of the drilled via holes is usually achieved by copper electroplating
Implementation Method 2
uses lasers to drill holes through the subsequently laid down dielectric substrate through to the latest metal layer
Data Source
AI summary
An array of chip sockets defined by an organic matrix framework surrounding sockets through the organic matrix framework and further comprising a grid of metal vias through the organic matrix framework. In an embodiment, a panel includes an array of chip sockets, each surrounded and defined by an organic matrix framework including a grid of copper vias through the organic matrix framework. The panel includes at least a first region with sockets having a set of dimensions for receiving one type of chip and a second region with sockets and another set of dimensions for receiving a second type of chip.