Interposer Redistribution Structure for High-Density I/O Fan-Out
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Solution Overview
Problem
The increasing density of input/output (I/O) pads on integrated circuit dies, resulting from smaller semiconductor sizes and integrated functions, poses challenges in die packaging, particularly in forming fan-out packages that redistribute I/O pads to a greater area.
Innovation Solution
A redistribution structure is formed using dielectric layers with varying properties, combining photosensitive and photoinsensitive molding compounds to reduce warpage and enhance mechanical and electrical performance, along with an interposer for efficient fan-out connections.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If integrated circuit dies are made smaller to increase I/O pad density, then the number of I/O pads per unit area increases, but the area available for I/O pads decreases
Solution Approach 1:
The patent employs an interposer substrate that redistributes I/O pads from the die surface to a larger area on the interposer, effectively moving the connection interface to another dimension (from the die plane to the interposer plane). This allows high I/O pad density on the die while maintaining adequate spacing on the interposer for packaging operations.
Solution Approach 2:
The interposer acts as an intermediary component between the integrated circuit die and the package substrate. It receives high-density I/O pads from the die and redistributes them to a larger area, mediating the contradiction between small die size and adequate I/O pad spacing for packaging.
2Quantity of substance
If fan-out packages are formed to redistribute I/O pads to a greater area, then the number of I/O pads on die surfaces can be increased, but the packaging complexity increases
Solution Approach 1:
The packaging system is segmented into distinct functional components: the integrated circuit die, the interposer substrate with redistribution layers, and the package substrate. This segmentation allows each component to be optimized independently, reducing overall packaging complexity while enabling high I/O pad counts through the interposer's redistribution capability.
3Stability of the object's composition
If dielectric layers with varying properties are combined to reduce warpage, then mechanical and electrical performance is enhanced, but manufacturing complexity increases
Solution Approach 1:
Different dielectric layers are used in specific locations within the interposer structure based on their local requirements. For example, first dielectric material is used in regions requiring low dielectric constant for signal integrity, while second dielectric material is used in regions requiring mechanical stability or different thermal properties. This local quality approach reduces warpage while managing manufacturing complexity through targeted material selection.
Data Source
AI summary
In an embodiment, a method includes: dispensing a first dielectric layer around and on a first metallization pattern, the first dielectric layer including a photoinsensitive molding compound; planarizing the first dielectric layer such that surfaces of the first dielectric layer and the first metallization pattern are planar; forming a second metallization pattern on the first dielectric layer and the first metallization pattern; dispensing a second dielectric layer around the second metallization pattern and on the first dielectric layer, the second dielectric layer including a photosensitive molding compound; patterning the second dielectric layer with openings exposing portions of the second metallization pattern; and forming a third metallization pattern on the second dielectric layer and in the openings extending through the second dielectric layer, the third metallization pattern coupled to the portions of the second metallization pattern exposed by the openings.