Interposer Molding for Planar Surface and Warpage Control
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Solution Overview
Problem
The existing semiconductor packaging methods using silicon interposers face issues such as thermal expansion mismatch leading to warpage, delamination, and increased process time due to multiple underfilling processes, which affect the reliability and efficiency of electrical connections.
Innovation Solution
A semiconductor package is fabricated using a carrier with interposers encapsulated by an encapsulant formed through a molding process, preventing warpage and eliminating the need for repeated underfilling, while ensuring a planar surface for semiconductor elements and maintaining electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If silicon interposers are used to overcome CTE mismatch, then CTE compatibility is improved, but warpage occurs during reflow process reducing planarity
Solution Approach 1:
The interposer structure is segmented into multiple layers including a support layer and a cap layer. The cap layer is specifically designed to cover and protect the top surface of the interposer, preventing warpage during reflow processes while maintaining CTE compatibility with the semiconductor chip.
Solution Approach 2:
The interposer is constructed as a composite structure with different materials having different CTE properties. The support layer and cap layer are made of materials selected to provide both CTE matching with the chip and resistance to warpage, creating a composite structure that balances thermal expansion characteristics.
2Reliability
If multiple underfilling processes are performed, then encapsulation is improved, but process time is significantly increased
Solution Approach 1:
Multiple underfilling processes are merged into a single underfilling operation. The cap layer structure enables this consolidation by providing a configuration where one underfilling process can simultaneously achieve the encapsulation effects that previously required multiple separate processes, thereby reducing total process time.
Solution Approach 2:
The cap layer is formed in advance before the final underfilling process. This preliminary structure preparation enables the subsequent underfilling to be more efficient and comprehensive, achieving multiple encapsulation goals in a single operation rather than requiring sequential processes.
3Reliability
If underfill is formed between interposer and packaging substrate, then encapsulation is improved, but underfill creeps up to contaminate RDL structure
Solution Approach 1:
The harmful creeping effect is extracted and eliminated by introducing the cap layer structure. The cap layer acts as a barrier that prevents the underfill from creeping up onto the RDL structure, thereby removing the contamination issue while preserving the beneficial encapsulation function.
Solution Approach 2:
The cap layer serves as an intermediary barrier between the underfill and the RDL structure. It mediates the interaction by allowing the underfill to perform its encapsulation function while blocking its harmful creeping motion, thus protecting the RDL from contamination.
Data Source
AI summary
A semiconductor package is provided, including: a carrier; at least an interposer disposed on the carrier; an encapsulant formed on the carrier for encapsulating the interposer while exposing a top side of the interposer; a semiconductor element disposed on the top side of the interposer; and an adhesive formed between the interposer and the semiconductor element. By encapsulating the interposer with the encapsulant, warpage of the interposer is avoided and a planar surface is provided for the semiconductor element to be disposed thereon, thereby improving the reliability of electrical connection between the interposer and the semiconductor element.