Interposer Semiconductor Package Structure for Compact Multi-Chip Routing
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Solution Overview
Problem
Current semiconductor packages face challenges in achieving improved electrical characteristics and compact size while maintaining manufacturing cost-effectiveness, particularly in integrating multiple semiconductor chips and capacitors within a compact structure.
Innovation Solution
The semiconductor package design incorporates an interposer substrate with a first and second redistribution substrate, an interposer molding layer, and a connection semiconductor chip, along with a capacitor chip, which are electrically connected through conductive posts and encapsulated by an interposer molding layer, allowing for horizontal spacing of semiconductor chips and enhanced electrical connectivity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Volume of moving object
If multiple semiconductor chips and capacitors are integrated within a compact structure, then the package size is reduced, but the electrical characteristics and power integrity deteriorate due to noise and connection reliability issues
Solution Approach 1:
An interposer substrate is introduced as an intermediary component between the package substrate and semiconductor chips. The interposer substrate includes first and second redistribution substrates with controlled impedance traces that act as signal integrity mediators, reducing noise and improving electrical characteristics while enabling compact chip arrangement
Solution Approach 2:
The patent transitions from planar two-dimensional chip arrangement to three-dimensional vertical stacking with the interposer substrate positioned between the package substrate and chips. This dimensional change allows better signal routing and noise isolation in the vertical dimension, improving power integrity while maintaining compact footprint
2Volume of moving object
If multiple semiconductor chips are integrated within a compact structure, then the package size is reduced, but the design flexibility is constrained due to space limitations
Solution Approach 1:
The interposer substrate is segmented into multiple functional layers including a first redistribution substrate and a second redistribution substrate, with separate regions dedicated to different chip types (semiconductor chips and capacitor chips). This segmentation allows independent optimization of each component's placement and electrical connections, enhancing design freedom within the compact structure
Solution Approach 2:
The interposer substrate serves multiple functions simultaneously: it acts as a mechanical support structure, provides electrical redistribution through controlled impedance traces, enables thermal management pathways, and facilitates precise positioning of multiple chip types. This multi-functionality increases design versatility without increasing package size
Data Source
AI summary
Disclosed is a semiconductor package comprising a package substrate, an interposer substrate on the package substrate and including a first redistribution substrate, a second redistribution substrate on a bottom surface of the first redistribution substrate, and an interposer molding layer between the first redistribution substrate and the second redistribution substrate, a connection substrate on the interposer substrate and having a connection hole that penetrates the connection substrate, a first semiconductor chip on the interposer substrate and in the connection hole, a second semiconductor chip on the interposer substrate, in the connection hole and horizontally spaced apart from the first semiconductor chip, and a connection semiconductor chip in the interposer molding layer and on the bottom surface of the first redistribution substrate.