Interposer Package Structure to Prevent Cracking and Delamination
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Solution Overview
Problem
The reliability of multi-die semiconductor packages is compromised due to challenges in packaging materials and arrangements, which affect the structural integrity and electrical connectivity of the packaged products.
Innovation Solution
A semiconductor package structure involving an interposer with semiconductor dies mounted on it, where a molding compound encapsulates the dies and laterally wraps around the interposer, and pre-cut lanes are formed to enhance structural support and prevent delamination, combined with a singulation process to create individual packages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional packaging materials and arrangements are used for multi-die packages, then manufacturing simplicity is maintained, but reliability and structural integrity are compromised due to cracking risks and delamination
Solution Approach 1:
The patent divides the packaging structure into distinct functional regions: a first packaging material layer positioned between adjacent semiconductor dies to provide mechanical support and prevent cracking, and a second packaging material layer positioned between the semiconductor dies and the substrate to ensure proper alignment and reduce delamination. This segmentation allows each layer to address specific reliability issues without requiring complete redesign of the entire packaging system.
Solution Approach 2:
The patent applies different packaging materials with specific properties to different locations within the package structure. The first packaging material is specifically positioned in regions where cracking prevention is critical (between adjacent dies), while the second packaging material is placed where alignment and adhesion are paramount (between dies and substrate). This local optimization of material properties enhances overall reliability without unnecessarily complicating the entire structure.
2Strength
If packaging materials are arranged to improve structural integrity, then cracking risks are reduced, but manufacturing complexity increases
Solution Approach 1:
The patent incorporates the first packaging material layer during the die attachment process itself, before subsequent packaging steps. This preliminary placement ensures that the structural support and crack prevention features are already in position to guide subsequent manufacturing steps, rather than requiring additional post-assembly operations to add structural reinforcement.
3Reliability
If a single packaging material is used for all regions, then manufacturing simplicity is maintained, but electrical connectivity and structural support are insufficient
Solution Approach 1:
The patent applies different packaging materials with specific properties to different locations within the package structure. The first packaging material is specifically positioned in regions where cracking prevention is critical (between adjacent dies), while the second packaging material is placed where alignment and adhesion are paramount (between dies and substrate). This local optimization of material properties enhances overall reliability without unnecessarily complicating the entire structure.
Data Source
AI summary
A semiconductor package and a manufacturing method thereof are provided. The semiconductor package includes at least one semiconductor die, an interposer, a molding compound and connectors. The interposer has a first surface, a second surface opposite to the first surface and sidewalls connecting the first and second surfaces. The at least one semiconductor die is disposed on the first surface of interposer and electrically connected with the interposer. The molding compound is disposed over the interposer and laterally encapsulates the at least one semiconductor die. The molding compound laterally wraps around the interposer and the molding compound at least physically contacts a portion of the sidewalls of the interposer. The connectors are disposed on the second surface of the interposer, and are electrically connected with the at least one semiconductor die through the interposer.