Interposer Passivation Structure for Low-Resistance Via Bonding
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Solution Overview
Problem
Existing semiconductor packaging technologies face challenges in achieving high integration density, reduced electrical resistance, and minimizing delamination risks in passivation films, particularly in advanced packaging systems like SoIC and CoWoS.
Innovation Solution
A simplified passivation film scheme for interposers with a single etch stop layer (ESL) and dielectric layer, reducing via length and electrical resistance, and minimizing delamination risk by ensuring a single interface, which is formed using specific materials and processes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a simplified passivation film scheme with single ESL and dielectric layer is used, then manufacturing complexity is reduced and productivity is improved, but via length reduction may compromise electrical connection reliability
Solution Approach 1:
The patent merges the ESL and dielectric layer into a simplified passivation film structure, combining protective and insulating functions into an integrated layer that reduces manufacturing steps while maintaining electrical connection integrity through optimized material composition and thickness control
Solution Approach 2:
The patent changes the physical parameters of the passivation film by controlling the thickness and material composition of the ESL and dielectric layer, optimizing the balance between via length reduction for lower resistance and sufficient coverage for reliable electrical connections
2Reliability
If via length is reduced to lower electrical resistance, then electrical performance is improved, but passivation film coverage may be compromised increasing delamination risk
Solution Approach 1:
The patent applies local quality by creating different functional zones within the passivation film structure, where the ESL provides localized protection at the via interface and the dielectric layer provides bulk insulation, optimizing both electrical performance and delamination resistance in different regions
Solution Approach 2:
The patent uses composite materials by combining ESL and dielectric layer with complementary properties, where the ESL offers etch resistance and localized protection and the dielectric layer provides low-k insulation and mechanical stability, achieving both low resistance and high stability
3Stability of the object's composition
If multiple ESL and dielectric layers are used in passivation film, then delamination resistance is improved, but manufacturing complexity and production time increase
Solution Approach 1:
The patent merges multiple protective and insulating functions into a simplified two-layer structure, combining the roles of multiple ESLs and dielectric layers into an integrated ESL-dielectric combination that maintains delamination resistance while reducing manufacturing complexity
Solution Approach 2:
The patent implements multi-functionality by designing the ESL to simultaneously provide etch resistance, mechanical support, and partial insulation, while the dielectric layer provides both electrical insulation and stress management, reducing the need for separate specialized layers
Data Source
AI summary
A semiconductor structure includes an interposer that includes: a substrate; a redistribution structure (RDS) on the substrate; a passivation film on the RDS, where the passivation film includes a first etch stop layer (ESL) on the RDS and a first dielectric layer on the first ESL; a via embedded in the passivation film, where the via is electrically coupled to a conductive feature of the RDS; a bonding film on the passivation film, where the bonding film includes a second ESL on the passivation film and a second dielectric layer on the second ESL; and a bonding pad and a first dummy bonding pad that are embedded in the bonding film, where the bonding pad is electrically coupled to the via, and the first dummy bonding pad is electrically isolated; and a die attached to the interposer, where a die connector of the die is bonded to the bonding pad.