Interposer RDL Packaging for Dense I/O and Electrical Performance
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Solution Overview
Problem
The increasing complexity and miniaturization of semiconductor devices pose challenges in processing and manufacturing, particularly in reducing the package size and maintaining electrical performance while accommodating the ever-increasing number of input/output connections.
Innovation Solution
The integration of through-silicon vias (TSVs) and redistribution layers (RDLs) in a fan-out wafer level package, along with conductive vias and interposer dies, allows for reduced pitch and improved electrical performance, and the use of testing structures for verification and yield enhancement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If through-silicon vias (TSVs) and redistribution layers (RDLs) are integrated in a fan-out wafer level package, then electrical performance is improved and pitch is reduced, but device complexity increases
Solution Approach 1:
The patent implements fan-out wafer level packaging by routing signals laterally through redistribution layers (RDLs) on the package substrate rather than directly vertically through TSVs. This dimensional change in signal routing allows multiple I/O connections to be distributed across a larger area, reducing pitch while maintaining electrical performance and managing complexity through spatial distribution.
Solution Approach 2:
The package substrate with RDLs serves as an intermediary between the semiconductor die and the external environment. The RDLs redistribute signals from TSV landing pads to external contact pads, acting as a mediator that decouples the complex TSV structure from the external I/O connections, thereby improving electrical performance while managing overall package complexity.
2Productivity
If the number of input/output connections is increased, then functional density is improved, but package size reduction becomes more difficult
Solution Approach 1:
The fan-out packaging architecture utilizes the planar dimension of the package substrate to distribute multiple I/O connections through RDLs. By routing signals laterally across the substrate surface rather than concentrating them vertically, the package can accommodate increased functional density while maintaining a compact overall size through efficient spatial utilization.
Solution Approach 2:
The package substrate is segmented into multiple RDL layers and regions, each handling specific signal routing functions. This segmentation allows high-density I/O connections to be organized and distributed across different areas and layers of the substrate, increasing functional density while managing the physical package size through systematic spatial distribution.
3Length of moving object
If geometric size is decreased, then miniaturization is achieved, but manufacturing complexity increases
Solution Approach 1:
The TSVs and RDLs are formed on the package substrate before the semiconductor die is mounted. This preliminary structuring of the packaging substrate allows for optimized signal routing and electrical performance to be established in advance, enabling miniaturization while managing manufacturing complexity through pre-fabricated interconnect structures that can be produced using standard semiconductor fabrication processes.
Data Source
AI summary
A method includes: forming an interposer die using a substrate, the interposer die including a plurality of conductive vias in the substrate; bonding the interposer die to a first redistribution layer (RDL); encapsulating the interposer die; forming a second RDL over the interposer die on a side opposite to the first RDL; bonding a first semiconductor die with one of the first RDL and the second RDL; and encapsulating the first semiconductor die.