Interposer Recess Structure for Thinner Semiconductor Package Cooling
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Solution Overview
Problem
Existing semiconductor packages face limitations in thickness increase, leading to inadequate heat dissipation characteristics and difficulty in improving thermal management due to the distance from the semiconductor chip's upper surface to the interposer substrate, which is typically 40 μm or more.
Innovation Solution
The semiconductor package incorporates a first recess in the interposer and a second recess in the interposer or package substrate, allowing for a reduced distance between the semiconductor chip and the interposer while maintaining overall package thickness, enhancing heat dissipation through vertical conductive structures and molding layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If the thickness of the semiconductor chip is increased to improve heat dissipation, then thermal characteristics are improved, but the overall package thickness increases
Solution Approach 1:
The package structure is segmented into multiple functional layers including the semiconductor chip, molding layer, interposer substrate, and circuit board. The interposer substrate is further segmented with recess portions that create stepped surfaces. This segmentation allows the semiconductor chip to have increased thickness for improved heat dissipation while the recess portions in the interposer substrate compensate for the increased height, maintaining the overall package thickness within limits.
Solution Approach 2:
The interposer substrate features localized recess portions at specific positions where semiconductor chips are mounted. These recess portions create local variations in height that allow the chip thickness to be increased in those specific areas while maintaining the overall package profile. The recess portions are strategically positioned to provide thermal management benefits without increasing the maximum package thickness.
2Reliability
If the distance from the semiconductor chip to the interposer substrate is increased to prevent mold void, then manufacturing reliability is improved, but heat dissipation characteristics deteriorate
Solution Approach 1:
The structure transitions from a fixed uniform distance to a dynamic stepped configuration. The molding layer thickness varies across different regions, being thinner in areas where recess portions are located and thicker in other areas. This dynamic thickness distribution allows the mold filling process to proceed without voids while maintaining minimal distance between the chip and interposer substrate for effective heat dissipation.
Solution Approach 2:
The solution moves from a one-dimensional uniform spacing approach to a three-dimensional stepped structure. By creating recess portions in the interposer substrate, the patent introduces vertical dimensionality variations that allow the molding layer to have different thicknesses in different regions. This enables the mold to fill properly without voids while keeping the heat dissipation path as short as possible.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design improves heat dissipation characteristics and electrical reliability by reducing the distance between the semiconductor chip and the interposer, preventing mold voids, and maintaining the package's thickness, thereby enhancing thermal management.
Implementation Method 1
a vertical conductive structure provided on the first package substrate and a side surface of the first semiconductor chip, and connecting the first package substrate and the interposer
Implementation Method 2
the first pad structure includes a recess, the connection terminal fills at least a portion of the recess
Data Source
AI summary
A semiconductor package includes a first package substrate, a first semiconductor chip provided on the first package substrate, an interposer provided on the first semiconductor chip, and a vertical conductive structure provided on the first package substrate and a side surface of the first semiconductor chip, and connecting the first package substrate and the interposer, the interposer includes a first recess vertically overlapping the first semiconductor chip in a lower portion of the interposer, and a lower surface of the interposer defining the first recess is higher than an upper surface of the vertical conductive structure.