Interposer-Based Semiconductor Package Testing Method
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Solution Overview
Problem
The existing methods for testing semiconductor packages are inefficient, as they require multiple electrical test steps and a substrate, leading to high fabrication costs and reduced throughput due to the mismatch of thermal expansion coefficients between semiconductor chips and substrates, which can cause reliability issues and warpage, and do not comply with compact-sized and low-profiled requirements for modern electronic products.
Innovation Solution
A method involving the use of an interposer with conductive elements on an adhesive layer, where semiconductor chips are tested directly without a substrate, using adhesive layer vias formed by thermal cautery or mechanical drilling, and the interposer is attached to a substrate via reflow, allowing for early detection of faulty components and reduced fabrication costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a substrate is used to dispose semiconductor chips, then the chips can be mounted and connected, but the mismatch of thermal expansion coefficients causes warpage and poor electrical contact
Solution Approach 1:
An interposer made of the same material as the semiconductor chip is introduced as an intermediary component between the chip and substrate. This interposer has a larger area than the chip, allowing it to absorb thermal expansion differences. The conductive bumps connect the chip to the interposer, eliminating direct chip-substrate contact and preventing warpage caused by CTE mismatch.
Solution Approach 2:
The area parameter of the mounting structure is changed from chip-size to interposer-size (larger area). This parameter change allows the thermal expansion stress to be distributed over a larger area, reducing the stress concentration and preventing warpage while maintaining electrical connectivity.
2Measurement precision
If multiple electrical test steps are performed with substrate, then testing can be conducted, but fabrication cost increases and throughput decreases
Solution Approach 1:
Electrical testing is performed on the semiconductor chip before it is permanently mounted on the substrate, while the chip is still attached to the interposer. This preliminary testing allows faulty chips to be identified and removed early, avoiding the need for complex post-assembly testing and rework, thereby increasing throughput and reducing costs.
Solution Approach 2:
The testing process is segmented into two stages: first testing the chip-interposer connection independently, then testing the complete assembly. This segmentation allows for targeted testing of critical interfaces without requiring the entire substrate assembly, reducing test time and complexity.
3Quantity of substance
If chips are disposed in two-dimension manner on substrate, then more chips can be mounted, but the substrate area increases violating compact requirements
Solution Approach 1:
The mounting arrangement transitions from a two-dimensional layout to a three-dimensional stacked configuration. Multiple semiconductor chips are vertically stacked on the interposer, utilizing the vertical dimension for expansion. This allows more chips to be mounted without increasing the substrate footprint, meeting compact size requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This method enables direct testing of interposers and semiconductor chips, reducing fabrication costs and equipment costs, and increases yield by alleviating warpage and allowing for efficient electrical testing without a substrate, thereby improving the reliability and compactness of semiconductor packages.
Implementation Method 1
adhesive layer vias formed by thermal cautery or mechanical drilling
Implementation Method 2
the interposer is attached to a substrate via reflow
Data Source
AI summary
A method of testing a semiconductor package is provided, including: disposing at least an interposer on a top surface of an adhesive layer, the interposer having a first surface and a second surface opposite to the first surface, a plurality of conductive elements disposed between the second surface of the interposer and the adhesive layer; disposing at least a semiconductor chip on the first surface of the interposer, and performing an electrical test on the semiconductor chip via the conductive elements, wherein if there are a plurality of semiconductor chips that are disposed on the first surface of the interposer, the step of disposing the semiconductor chip and performing the electrical test on the semiconductor chip is iterated; and removing the adhesive layer. By using the method, the fabrication cost and equipment cost of the semiconductor package are reduced, and product yield is increased.