Interposer Boundary-Scan Circuit for Single-TMS Stack Testing
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Solution Overview
Problem
The IEEE 1149.1 standard for boundary scan testing in integrated circuits (ICs) is not widely used in memory, analog, and mixed signal ICs due to increased package size and decreased input/output performance, and existing access methods for stacked die configurations require multiple TMS signals and lengthen test times by shifting data through local inputs and outputs.
Innovation Solution
An interposer is enhanced to include IEEE 1149.1 TAP circuitry, allowing for serial access of all TAPs with a single TMS signal and eliminating the need for multiple TMS signals, while optimizing test operations by only testing connections between the interposer and substrate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If IEEE 1149.1 boundary scan circuitry is included in ICs, then boundary scan testing capability is improved, but package size increases and input/output performance decreases
Solution Approach 1:
The patent divides the boundary scan testing system into separate components: the IC under test retains only minimal boundary scan cells, while the interposer contains the majority of the boundary scan functionality including the TAP controller and boundary scan register. This segmentation allows the IC to remain small while still achieving full boundary scan testing capability through the interposer's infrastructure.
2Reliability
If IEEE 1149.1 boundary scan circuitry is included in ICs, then boundary scan testing capability is improved, but input/output performance decreases due to boundary scan cell multiplexers
Solution Approach 1:
The patent separates the TAP controller and boundary scan register from the IC's I/O path by placing them in the interposer. This segmentation eliminates the need for multiplexers within the IC that would slow down I/O operations, as the boundary scan functionality is accessed through the interposer's dedicated test interface rather than through the IC's functional I/O paths.
3Adaptability or versatility
If multiple TMS signals are used to access TAPs in stacked die configurations, then all TAPs can be accessed, but test complexity and test time increase
Solution Approach 1:
The patent merges multiple TAP controllers into a single unified TAP controller located in the interposer. This single TAP controller can serially access multiple boundary scan registers across stacked die through the interposer's routing infrastructure, eliminating the need for multiple independent TMS signals and reducing test complexity while maintaining full access capability.
4Reliability
If data is shifted through local inputs and outputs for testing, then complete testing can be performed, but test time increases
Solution Approach 1:
The patent extracts the boundary scan register and TAP controller from the individual ICs and places them in the interposer. This extraction allows test data to be loaded once into the interposer's boundary scan register and then distributed to multiple ICs simultaneously through the interposer's routing, rather than requiring separate data loading for each IC, thereby reducing redundant testing and overall test time.
Data Source
AI summary
The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.