Interposer TAP Circuitry for Stacked-Die Interconnect Testing
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Solution Overview
Problem
The implementation of IEEE 1149.1 boundary scan circuitry in integrated circuits (ICs) is hindered in memory and mixed-signal ICs due to increased package size and decreased input/output performance, and existing access methods require multiple TMS signals and sequential selection of TAPs, leading to inefficiencies in testing and debugging.
Innovation Solution
Incorporating IEEE 1149.1 TAP circuitry into interposers allows for improved testing and debugging by eliminating the need for multiple TMS signals and sequential TAP selection, enabling serial access to multiple TAPs with a single TMS signal and reducing test time by focusing only on interconnects between stacked dies and substrates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If IEEE 1149.1 boundary scan circuitry is included in integrated circuits, then testing and debugging capabilities are improved, but package size increases and input/output performance decreases
Solution Approach 1:
The patent introduces an interposer as an intermediary component between the substrate and stacked dies. The interposer contains the IEEE 1149.1 TAP circuitry and boundary scan cells, serving as a mediator that provides testing capabilities without requiring the dies themselves to contain this circuitry. This allows the TAP interface to be accessed through the interposer while the actual testing function is distributed across the interposer and dies.
2Reliability
If multiple TAPs are accessed sequentially using multiple TMS signals, then each TAP can be tested individually, but test time increases and access complexity increases
Solution Approach 1:
The patent merges multiple TAP control functions into a single unified TAP interface located in the interposer. Instead of having separate TMS signals for each die's TAP, the interposer's TAP receives a single TMS signal and internally routes it to the appropriate die's TAP based on the current selection state. This consolidation reduces the number of external TMS signals needed and allows sequential access to multiple TAPs through a single interface, significantly reducing test time and access complexity.
3Adaptability or versatility
If boundary scan cells are placed in every die, then each die has independent testing capability, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent segments the boundary scan functionality by separating the TAP interface logic from the boundary scan cells. The TAP interface is located in the interposer, while the boundary scan cells are distributed in the dies. This segmentation allows each die to contain only the necessary boundary scan cells without the full TAP interface complexity, reducing individual die complexity while maintaining the ability to perform boundary scan testing through the interposer's centralized TAP.
Data Source
AI summary
The disclosure describes a novel method and apparatus for improving interposers that connected stacked die assemblies to system substrates. The improvement includes the addition of IEEE 1149.1 circuitry within interposers to allow simplifying interconnect testing of digital and analog signal connections between the interposer and system substrate it is attached too. The improvement also includes the additional 1149.1 controlled circuitry that allows real time monitoring of voltage supply and ground buses in the interposer. The improvement also includes the additional of 1149.1 controlled circuitry that allows real time monitoring of functional digital and analog input and output signals in the interposer. The improvement also provides the ability to selectively serially link the 1149.1 circuitry in the interposer with 1149.1 circuitry in the die of the stack.