Interposer Thin-Film Capacitor Layout for Compact Semiconductor Packages

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Solution Overview

Problem

Semiconductor packages face challenges in achieving high performance and high capacitance while reducing size and weight, with existing designs compromising reliability and efficiency.

Innovation Solution

A semiconductor package design incorporating a package substrate, interposer die with a redistribution structure, passive elements, and semiconductor chips, where the passive elements are thin film capacitors with a crystalline dielectric film, and are electrically connected through redistribution layers, allowing for improved power integrity and efficient use of space.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Volume of moving object

If the passive element thickness is reduced to 50 μm or less, then the package size and weight are reduced, but the manufacturing precision and reliability become more challenging

Engineering Contradiction:

Improvepackage sizeVSAvoidpassive element thickness control

Core Design Contradiction:

Volume of moving objectVSManufacturing precision

Solution Approach 1:

The patent specifies a precise thickness parameter range (50 μm or less) for the passive element and uses crystalline structure formation in the dielectric film to achieve consistent dimensional control. This parameter optimization allows miniaturization while maintaining manufacturing feasibility through controlled crystal growth processes.

Inventive Principle:

Principle #35Parameter changes

Solution Approach 2:

The passive element employs a composite structure with a crystalline dielectric film layer and electrode layers, where the crystalline structure provides mechanical strength and dimensional stability despite the reduced overall thickness. This composite approach enables both size reduction and reliability maintenance.

Inventive Principle:

Principle #40Composite materials

2Quantity of substance

If passive elements are integrated into the interposer die with thin film structure, then the capacitance density is improved, but the electrical connection reliability becomes more critical

Engineering Contradiction:

Improvecapacitance densityVSAvoidelectrical connection stability

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The passive element is nested within the interposer die structure, with the thin film capacitor integrated into the redistribution layer stack. This nested integration achieves high capacitance density by utilizing the vertical space within the interposer while maintaining electrical connections through the redistribution network.

Inventive Principle:

Principle #7Nested doll (Nesting)

Solution Approach 2:

The redistribution layers serve as intermediary conductors that electrically connect the thin film passive elements to the package substrate and semiconductor chips. This intermediary structure enables reliable electrical connections despite the miniaturized passive element design.

Inventive Principle:

Principle #24Intermediary (Mediator)

3Reliability

If the dielectric film has a crystalline structure, then the electrical performance is improved, but the manufacturing complexity increases

Engineering Contradiction:

Improveelectrical performanceVSAvoidcrystalline structure formation process

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The dielectric film undergoes a phase transition to form a crystalline structure, which provides superior electrical performance with lower loss and higher stability. This phase transition is controlled during the fabrication process to achieve the desired crystalline morphology without excessive manufacturing complexity.

Inventive Principle:

Principle #36Phase transitions

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The design enhances reliability and performance by optimizing the integration of passive elements, enabling high capacitance and reduced size, while maintaining efficient electrical connections and power integrity.

Implementation Method 1

a passive element in the interposer die, where the passive element is electrically connected to the redistribution layers, the passive element including a first electrode, a dielectric film on the first electrode, and a second electrode on the dielectric film

Methodology Applied

Scientific EffectCapacitance: Capacitance

Implementation Method 2

At least a portion of the dielectric film of the passive element may have a crystalline structure

Methodology Applied

Scientific EffectCrystalline structure: Crystallisation

Data Source

PatentUS20250365996A1Semiconductor package

Publication Date: 2025.11.27 SAMSUNG ELECTRONICS CO LTD

AI summary

A semiconductor package includes a package substrate, an interposer die on the package substrate, the interposer die including a redistribution structure, the redistribution structure including an insulating layer including an organic material, and redistribution layers in the insulating layer, a passive element in the interposer die, where the passive element is electrically connected to the redistribution layers, the passive element including a first electrode, a dielectric film on the first electrode, and a second electrode on the dielectric film, and semiconductor chips on an upper surface of the insulating layer and spaced apart from each other in a horizontal direction on the interposer die, where the semiconductor chips are electrically connected to the package substrate through the redistribution layers. A thickness of the passive element is about 50 μm or less, and at least a portion of the dielectric film of the passive element has a crystalline structure.