Interposer Package Structure With TIM Cooling for Stacked Dies
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Solution Overview
Problem
Existing semiconductor package structures struggle with effective heat dissipation, particularly in advanced IC devices with vertically stacked and compactly packaged configurations, which can lead to performance degradation or physical damage due to inadequate thermal management.
Innovation Solution
The proposed IC package structure includes a package substrate, an interposer, first and second dies connected by micro bumps, a thermal interface material, and a heat sink, with optional backside metallization, where the dies have varying heights and micro bumps are formed to facilitate improved heat dissipation through local thinning processes and differential micro bump heights.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If vertically stacked and compactly packaged configurations are used to increase functional density, then device density and production efficiency are improved, but heat dissipation capability deteriorates
Solution Approach 1:
The patent introduces a lateral heat dissipation dimension by extending heat dissipation fins from the side walls of the encapsulant rather than relying solely on vertical top-surface fins. This side-heat-dissipation pathway adds a new dimensional route for thermal energy escape, enabling effective heat management in vertically stacked high-density configurations where traditional top-surface dissipation becomes insufficient.
2Device complexity
If vertically stacked configurations are used to maximize functional density, then device integration is improved, but thermal management capability deteriorates
Solution Approach 1:
The heat dissipation system is segmented into multiple independent pathways: top-surface fins for vertical heat dissipation and side-heat-dissipation fins for lateral heat dissipation. This segmentation allows thermal energy to be dissipated through multiple separate routes, preventing thermal bottlenecks and ensuring reliable thermal management even as device integration complexity increases with vertical stacking.
3Ease of manufacture
If conventional package structures are used, then manufacturing simplicity is maintained, but heat dissipation efficiency deteriorates
Solution Approach 1:
The side-heat-dissipation fins are nested within or integrated with the encapsulant structure itself, rather than being separate external components. This nesting approach allows the heat dissipation functionality to be embedded within the existing package architecture, maintaining manufacturing simplicity while significantly improving heat dissipation efficiency through the additional lateral heat transfer pathway.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances heat dissipation efficiency, allowing for increased device density, scalability, and design flexibility while preventing performance degradation and physical damage in high-performance computing and artificial intelligence applications.
Implementation Method 1
a thermal interface material, and a heat sink, with optional backside metallization, where the dies have varying heights and micro bumps are formed to facilitate improved heat dissipation
Data Source
AI summary
A method includes providing an interposer structure including conductive paths, forming micro bumps over the interposer structure and connected to the conductive paths, bonding a first die and a second die onto the micro bumps, forming a molding compound over and around the first die and the second die, performing a planarization process to expose a top surface of the second die, forming a trench in the molding compound to expose a top surface of the first die, forming a thermal interface material (TIM) layer in the trench and over the top surface of the second die, bonding the interposer structure to a substrate, and attaching a heat sink onto the TIM layer. The first die has a first height and the second die has a second height greater than the first height.