Interposer TSVs with Varying Sizes for 3DIC Integration
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Solution Overview
Problem
The formation of through-silicon vias (TSVs) in three-dimensional integrated circuits (3DICs) after the front-end-of-line (FEOL) and back-end-of-line (BEOL) processes leads to yield loss and prolonged manufacturing cycle time, as well as limitations in integration density and increased interconnections causing circuit RC delay and power consumption.
Innovation Solution
A novel 3DIC structure featuring an interposer with through-substrate vias (TSVs) of varying sizes, where large TSVs and small TSVs are formed with different horizontal dimensions and lengths, allowing for efficient electrical coupling and reduced manufacturing complexity by controlling TSV sizes through etching processes, and forming interconnect structures over the substrate and dielectric layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If TSVs are formed in device dies after FEOL and BEOL processes, then electrical connections between stacked dies are achieved, but yield loss occurs and manufacturing cycle time is prolonged
Solution Approach 1:
The patent forms TSVs in the interposer substrate before bonding the device dies to it. This preliminary formation of TSVs allows the interposer to serve as a pre-configured interconnection structure, enabling subsequent dies to be bonded without requiring TSV formation after die fabrication. This resolves the contradiction by achieving reliable electrical connections through pre-formed TSVs while avoiding the yield loss and cycle time extension associated with post-die TSV formation.
2Quantity of substance
If more devices are integrated into one chip, then integration density improves, but the number and length of interconnections increases causing increased RC delay and power consumption
Solution Approach 1:
The patent transitions from two-dimensional planar integration to three-dimensional stacked integration using an interposer structure. Multiple dies are vertically stacked and connected through TSVs, enabling significant increases in integration density without proportionally increasing interconnection length. The vertical stacking approach reduces the horizontal distance signals must travel, thereby reducing RC delay and power consumption while achieving higher device counts.
3Ease of manufacture
If TSVs of uniform size are used in interposers, then manufacturing process is simplified, but flexibility in connecting dies with different dimensions is limited
Solution Approach 1:
The patent implements TSVs with varying sizes at different locations within the interposer substrate. Each TSV size is optimized for its specific function and the dimensions of the dies it connects. This local differentiation allows the interposer to accommodate dies with different footprints and I/O requirements while maintaining manufacturing feasibility through a controlled variety of TSV dimensions rather than complete uniformity.
Data Source
AI summary
A device includes an interposer including a substrate having a top surface and a bottom surface. A plurality of through-substrate vias (TSVs) penetrates through the substrate. The plurality of TSVs includes a first TSV having a first length and a first horizontal dimension, and a second TSV having a second length different from the first length, and a second horizontal dimension different from the first horizontal dimension. An interconnect structure is formed overlying the top surface of the substrate and electrically coupled to the plurality of TSVs.