Interposer Chip TSVs Reduce Voltage Droop in High-Frequency Processors

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Solution Overview

Problem

Current semiconductor technologies face challenges in efficient power delivery and accurate voltage regulation due to increasing transient power demands and power-supply noise as processor clock speeds rise, leading to significant voltage droop issues.

Innovation Solution

A chip package design that includes an interposer chip with through-substrate vias (TSVs) electrically coupling a voltage regulator module (VRM) proximate to the processor, reducing voltage droop by providing improved power regulation accuracy and efficiency through the use of transient VRMs and advanced packaging technologies.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If the processor clock speed increases to improve processing performance, then the processing capability is improved, but the transient power demands and power-supply noise increase causing voltage droop

Engineering Contradiction:

Improveprocessing capabilityVSAvoidvoltage regulation

Core Design Contradiction:

ProductivityVSReliability

Solution Approach 1:

An interposer chip is introduced as an intermediary component between the processor and the circuit board. The interposer includes through-substrate vias (TSVs) that provide low-inductance electrical connections, acting as a mediator to reduce the harmful effects of transient power demands and voltage droop while maintaining high processing speeds

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If the VRM is placed far from the processor, then the layout flexibility is improved, but the voltage droop increases due to longer current paths

Engineering Contradiction:

Improvelayout flexibilityVSAvoidvoltage droop

Core Design Contradiction:

Adaptability or versatilityVSObject-affected harmful factors

Solution Approach 1:

The interposer chip enables the VRM to be positioned in a different spatial dimension relative to the processor. By using vertical through-substrate vias in the interposer, the electrical connection path is shortened in the vertical dimension while allowing horizontal layout flexibility, effectively reducing voltage droop without constraining the VRM placement

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Ease of manufacture

If traditional packaging methods are used, then the manufacturing simplicity is maintained, but the parasitic inductance increases reducing power delivery efficiency

Engineering Contradiction:

Improvemanufacturing simplicityVSAvoidpower delivery efficiency

Core Design Contradiction:

Ease of manufactureVSLoss of energy

Solution Approach 1:

The invention changes the physical parameters of the electrical connection path by using through-substrate vias with controlled dimensions and materials. This modifies the inductance and resistance parameters of the power delivery path, reducing parasitic effects while maintaining manufacturing feasibility through established TSV fabrication processes

Inventive Principle:

Principle #35Parameter changes

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The solution effectively reduces voltage droop and enhances transient voltage regulation, enabling high-frequency processor operation with improved power delivery and reduced parasitics, thus addressing the limitations of traditional packaging methods.

Implementation Method 1

The interposer chip includes through-substrate vias (TSVs) electrically coupling the first electrical connectors to the second electrical connectors

Methodology Applied

Scientific EffectElectrical Conduction: Conduction (electrical)

Implementation Method 2

the VRM is electrically coupled to the processor by the interposer chip, and is proximate to the processor in the chip package, thereby reducing voltage droop

Methodology Applied

Scientific EffectVoltage Regulation:

Implementation Method 3

the chip package includes a thermal cooling mechanism thermally coupled to a second surface of the processor

Methodology Applied

Scientific EffectThermal Conduction: Conduction (thermal)

Data Source

PatentUS8982563B2Chip package to support high-frequency processors

Publication Date: 2015.03.17 ORACLE INT CORP

AI summary

A chip package includes a processor, an interposer chip and a voltage regulator module (VRM). The interposer chip is electrically coupled to the processor by first electrical connectors proximate to a surface of the interposer chip. Moreover, the interposer chip includes second electrical connectors proximate to another surface of the interposer chip, which are electrically coupled to the first electrical connectors by through-substrate vias (TSVs) in the interposer chip. Note that the second electrical connectors can electrically couple the interposer chip to a circuit board. Furthermore, the VRM is electrically coupled to the processor by the interposer chip, and is proximate to the processor in the chip package, thereby reducing voltage droop. For example, the VRM may be electrically coupled to the surface of the interposer chip, and may be adjacent to the processor. Alternatively, the VRM may be electrically coupled to the other surface of the interposer chip.