Interposer Wafer Bonding via TSV Grinding
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Solution Overview
Problem
Conventional methods for manufacturing three-dimensional integrated circuits (3DICs) require two carriers for bonding dies onto interposers, leading to high manufacturing costs due to multiple mounting and de-mounting steps.
Innovation Solution
A method where an interposer wafer with through-substrate vias is used, allowing dies to be bonded on one surface, with grinding to expose vias and forming metal bumps for electrical coupling, potentially eliminating the need for additional carriers by using a single carrier or no carrier at all.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If two carriers are used for bonding dies onto interposer wafer, then dies can be bonded onto interposer wafer, but manufacturing cost increases due to multiple mounting and de-mounting steps
Solution Approach 1:
The patent extracts and removes the carrier from the bonding process entirely. By forming bumps directly on the interposer wafer substrate after die bonding, the carrier is no longer needed for supporting the interposer during processing, thereby eliminating the complexity and cost associated with multiple carriers and their mounting/demounting steps.
Solution Approach 2:
The patent performs preliminary actions by forming the bump structure on the interposer wafer before die bonding. The interconnect structure is formed on the interposer substrate, and bumps are prepared in advance, allowing dies to be bonded directly without requiring carrier support. This resequencing eliminates the need for subsequent carrier removal steps.
2Productivity
If two carriers are mounted on opposite sides of interposer wafer, then dies can be bonded, but process time increases due to multiple mounting and de-mounting steps
Solution Approach 1:
The carrier is extracted and removed from the process flow. By forming bumps directly on the interposer wafer substrate after die bonding, the patent eliminates the time-consuming steps of mounting and demounting carriers, thereby reducing total process time and increasing throughput.
Solution Approach 2:
The interconnect structure and bump formations are performed as preliminary actions before die bonding. This resequencing allows the interposer to be prepared in advance without carrier support, and eliminates subsequent carrier removal steps, thereby reducing overall process time.
3Ease of manufacture
If substrate is thinned before bonding dies, then TSVs are exposed, but manufacturing complexity increases due to additional processing steps
Solution Approach 1:
The patent performs substrate thinning as a preliminary action before die bonding, exposing the TSVs in advance. This allows the interconnect structure to be formed directly on the exposed TSVs without requiring subsequent carrier support or additional thinning steps after bonding, thereby simplifying the overall process while maintaining precision.
Data Source
AI summary
A method includes providing an interposer wafer including a substrate, and a plurality of through-substrate vias (TSVs) extending from a front surface of the substrate into the substrate. A plurality of dies is bonded onto a front surface of the interposer wafer. After the step of bonding the plurality of dies, a grinding is performed on a backside of the substrate to expose the plurality of TSVs. A plurality of metal bumps is formed on a backside of the interposer wafer and electrically coupled to the plurality of TSVs.