Interspersed Multi-Processor Array DMA-FIFO Architecture
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Solution Overview
Problem
Existing multi-processor systems face challenges in efficiently managing data communication and memory access due to internal delays and increased latency with more components, which affects computational throughput and energy efficiency.
Innovation Solution
The proposed solution involves a multi-processor array architecture that intersperses processing elements with data memory routers and direct memory access engines, enabling efficient data transfer and communication through configurable communication elements and a high-bandwidth interconnection network.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If more computational components are added to increase processing capability, then computational throughput is improved, but average latency increases due to more components and longer communication paths
Solution Approach 1:
The system is divided into multiple processing elements (PEs) organized in a two-dimensional array, each capable of independent operation. This segmentation allows parallel processing of data blocks, increasing overall throughput while keeping individual PE communication distances short, thus maintaining low latency for each processing unit
Solution Approach 2:
Processing elements are arranged in a two-dimensional spatial array rather than a linear or hierarchical structure. This dimensional arrangement optimizes the balance between communication distance and processing capacity, allowing each PE to access neighboring elements with minimal latency while collectively providing high computational throughput through parallel operations across the two-dimensional grid
2Loss of time
If component size is reduced to decrease latency, then signal travel time is reduced, but manufacturing precision requirements increase
Solution Approach 1:
The system employs dynamic configuration capabilities where processing elements and communication pathways can be reconfigured based on computational requirements. This allows the system to optimize performance without requiring fixed, ultra-precise physical layouts, as logical reconfiguration can compensate for manufacturing variations and achieve optimal latency-performance balance
3Productivity
If more processing elements are integrated on a single chip to increase parallelism, then computational capability is improved, but energy consumption increases
Solution Approach 1:
Each processing element is designed with localized resources including on-chip memory and communication interfaces, reducing the need for long-distance data transfers across the chip. This localizes data access and computation, minimizing energy consumption for data movement while maintaining high parallel processing capability through the distributed architecture
Solution Approach 2:
The system introduces on-chip memory and communication buffers as intermediaries between processing elements and external memory systems. These intermediaries reduce the frequency and distance of data transfers, significantly lowering energy consumption while enabling sustained high-throughput parallel processing by keeping data locally available to multiple PEs
Data Source
AI summary
Embodiments of a multi-processor array are disclosed that may include a plurality of processors, local memories, configurable communication elements, and direct memory access (DMA) engines, and a DMA controller. Each processor may be coupled to one of the local memories, and the plurality of processors, local memories, and configurable communication elements may be coupled together in an interspersed arrangement. The DMA controller may be configured to control the operation of the plurality of DMA engines.