Inverted Gate 2D Transistors for High-Density 3D Stacking
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Solution Overview
Problem
Current semiconductor manufacturing techniques face challenges in advancing beyond planar devices, particularly in achieving high-density three-dimensional (3D) stacking of 2D semiconductor devices while maintaining cost-effectiveness and performance.
Innovation Solution
The use of 2D materials such as WS2, WSe2, MoS2, and others, combined with an inverted gate electrode structure, allows for the fabrication of 3D devices by stacking 2D semiconductor layers, enabling vertical integration of transistors and other semiconductor components.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional 2D fabrication techniques are used to manufacture transistors on a single active device plane, then the manufacturing process is simple and well-established, but the transistor density per unit area is limited
Solution Approach 1:
The patent transitions from 2D planar fabrication to 3D vertical stacking by forming gate electrodes both above and below the 2D semiconductor channel. This dimensional change allows multiple transistor layers to be stacked vertically, dramatically increasing transistor density per unit area while maintaining compatibility with conventional fabrication processes
Solution Approach 2:
The fabrication process is segmented into distinct stages: forming bottom gate electrodes, depositing 2D semiconductor layers, forming top gate electrodes, and creating source/drain regions. This segmentation allows each step to be optimized independently while maintaining overall process simplicity
2Productivity
If 3D stacking of 2D semiconductor devices is implemented to increase transistor density, then high-density circuits can be achieved, but the fabrication process becomes more complex and costly
Solution Approach 1:
The patent employs universal fabrication techniques that work for both 2D and 3D devices, including chemical vapor deposition for 2D semiconductor growth, sputtering for metal gate electrode formation, and standard lithography for patterning. This universality allows 3D stacking to be achieved without requiring entirely new manufacturing processes
Solution Approach 2:
Bottom gate electrodes are formed and prepared in advance before the 2D semiconductor layers are deposited. This preliminary action simplifies subsequent processing steps and enables better process control during the 3D stacking fabrication sequence
3Manufacturing precision
If gate electrodes are formed after source and drain electrodes in conventional processes, then the manufacturing sequence is straightforward, but achieving perfectly planar 2D channel regions becomes difficult
Solution Approach 1:
The patent inverts the conventional electrode formation sequence by forming gate electrodes before source and drain electrodes. This inversion allows the 2D semiconductor channel to be deposited as a continuous planar layer across the entire substrate, ensuring uniform channel regions while simplifying the overall fabrication sequence
Data Source
AI summary
A semiconductor device may include a first dielectric layer, a first gate electrode, a first gate dielectric layer, a first source electrode, a first drain electrode, and a first two-dimensional (2D) semiconductor layer. The first dielectric layer may have a first top surface. The first gate electrode may extend from the first top surface into the first dielectric layer. The first gate dielectric layer may be disposed on the first gate electrode and have a second top surface. The first source electrode may extend from the second top surface, through the first gate dielectric layer and into the first dielectric layer. The first drain electrode may extend from the second top surface, through the first gate dielectric layer and into the first dielectric layer. The first 2D semiconductor layer may be disposed on the first gate dielectric layer.