Inverter Transistor Switching Timing for Miller Charge Detection
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Solution Overview
Problem
Inverters with silicon carbide transistors face challenges in maintaining even load distribution across transistors due to aging and manufacturing tolerances, leading to asymmetrical current distribution and accelerated transistor aging.
Innovation Solution
The inverter employs a method involving two switching operations to discharge and maintain the parasitic capacitance of a high-side transistor, allowing for the determination of a characteristic operating parameter based on the time difference between these operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If gate-source voltage is sampled over time to calculate Miller charge, then operating parameters can be determined, but measurement inaccuracies occur and additional monitoring triggers are required
Solution Approach 1:
The patent extracts the Miller charge measurement from the complex voltage sampling process by utilizing the naturally occurring voltage plateau during transistor switching. Instead of sampling gate-source voltage over time and calculating Miller charge, the method directly observes the plateau voltage level, which inherently represents the Miller charge state. This eliminates the need for additional monitoring triggers and complex sampling operations while maintaining measurement accuracy.
2Power
If transistors are used in parallel configurations, then current capacity increases, but asymmetrical current distribution occurs due to different operating parameters
Solution Approach 1:
The patent implements feedback by measuring the actual operating parameters (Miller charge, turn-on time, turn-off time) of each transistor in the parallel configuration and using this information to adjust the control signals. The control electronics modify the switching timing and duration for each transistor based on its individual characteristics, ensuring that all transistors share the load evenly despite manufacturing tolerances and aging effects.
3Loss of information
If gate-source voltage is monitored during switch-on operation, then switching behavior can be analyzed, but parasitic effects cannot be inferred
Solution Approach 1:
The patent uses the drain-source voltage plateau as an intermediary indicator that indirectly reveals parasitic capacitance effects. During the Miller plateau phase, the drain-source voltage remains constant while the gate charge is being stored in the parasitic capacitances. By monitoring this plateau voltage and its duration, the method infers information about parasitic capacitances without directly measuring them or complicating the gate-source voltage monitoring.
4Duration of action of moving object
If transistor aging is not compensated, then inverter operation continues, but load asymmetry accelerates transistor degradation
Solution Approach 1:
The patent implements periodic measurement of transistor operating parameters during normal operation. At predetermined intervals, the control electronics perform measurements of Miller charge, turn-on time, and turn-off time for each transistor. Based on these periodic measurements, the control signals are adjusted to compensate for aging effects, ensuring that load distribution remains balanced throughout the inverter's operational life and preventing accelerated degradation of any individual transistor.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables accurate determination of the Miller charge and capacitance of the transistor, facilitating more precise control over switching operations and improving load distribution, thereby extending the lifespan of the transistors.
Implementation Method 1
a parasitic capacitance of the first transistor is discharged during the first switching operation
Data Source
AI summary
An inverter. The inverter includes a first and second transistors, which are a high-side transistor and a low-side transistor of the inverter, and control electronics configured to trigger a first switching operation, in which the first transistor is switched on, wherein the second transistor is in a switched-off state, wherein a parasitic capacitance of the first transistor is discharged during the first switching operation, to trigger a second switching operation, in which the first transistor is switched off or switched on again, wherein the second transistor simultaneously remains in the switched-off state, wherein the parasitic capacitance of the first transistor is already discharged in the second switching operation, to record a time difference which describes a difference between a duration of the first switching operation and a duration of the second switching operation, and to determine a characteristic operating parameter of the first transistor based on the time difference.