I/O Block Placement Optimizing Wire Length and Bank Count
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Solution Overview
Problem
The placement of input/output (I/O) blocks on integrated circuit devices is challenging due to varying I/O standards and their integration into buses, affecting routing within the device and on connected circuit boards, with existing methods struggling to optimize placement while adhering to banking rules and minimizing wire length.
Innovation Solution
A method that modifies I/O standards to include bus information, creates I/O groups, and uses Integer Linear Programming (ILP) to assign I/O blocks to sites, optimizing placement to minimize the number of I/O banks and adhere to banking rules, while utilizing simulated annealing to generate a legal and efficient I/O placement.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If I/O blocks are placed without considering bus information, then placement process is simpler, but routing complexity increases and wire length increases
Solution Approach 1:
The patent applies preliminary action by modifying I/O standards to include bus information before the placement process begins. This allows the placement algorithm to pre-identify which I/O blocks belong to the same bus and should be grouped together, thereby simplifying subsequent routing operations and reducing wire length without making the placement process itself overly complex.
2Productivity
If I/O blocks are placed to minimize wire length, then routing efficiency improves, but adherence to banking rules becomes more difficult
Solution Approach 1:
The patent changes the parameters of the I/O standard by adding bus information (bus ID, bus name) to each I/O block. This parameter enrichment enables the placement algorithm to simultaneously optimize for wire length minimization while maintaining compliance with banking rules, as the additional parameters provide the constraints needed to guide the optimization process.
3Area of stationary object
If I/O blocks with different I/O standards are placed together, then I/O site utilization increases, but routing complexity on circuit board increases
Solution Approach 1:
The patent applies segmentation by dividing I/O blocks into distinct groups based on their bus affiliation. By creating I/O groups where blocks belonging to the same bus are clustered together, the patent reduces circuit board routing complexity while still achieving high I/O site utilization through the use of Integer Linear Programming to optimize the overall placement configuration.
Data Source
AI summary
A method of placing input/output blocks on an integrated circuit device is described. The method may comprise receiving a circuit design having a plurality of input/output blocks to be placed at input/output sites of the integrated circuit device; modifying, for each input/output block of the circuit design, an input/output standard for the input/output block to include bus information; assigning, for each input/output block of the circuit design, an input/output site for the input/output block; and generating an input/output placement for the input/output blocks of the circuit design. A computer product is also disclosed.