I/O Control Circuit for Reduced Pin Count Semiconductor Testing
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Reduced pin count testing in semiconductor devices with large pin counts, such as digital system-on-a-chip processors, fails to apply electrical stress to all pins, limiting test throughput and efficiency, especially when transitioning to in-situ burn-in, and existing split testing methods do not fully stress all device pins.
Innovation Solution
An input/output control circuit with serially connected latched drivers and analog-to-digital converters that fan out high-speed test signals to test a larger number of device pins, allowing reduced pin count testing to function like full pin count testing by stimulating and reading data from all pins, thereby enabling electrical stress and improved throughput.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If reduced pin count testing is used to lower test cost and improve throughput, then test throughput is improved, but electrical stress cannot be applied to all pins
Solution Approach 1:
The patent introduces an I/O control circuit as an intermediary between the tester and the device pins. This circuit includes a driver section that can selectively drive pins and a sense section that can read from pins, allowing the tester to indirectly control and test all pins through a reduced physical connection count. The control circuit acts as a mediator that expands the functional capability beyond the physical pin count.
Solution Approach 2:
The I/O control circuit is designed to perform multiple functions through a reduced set of connections. The driver section can drive any pin, and the sense section can read from any pin, making the reduced connection set universal for controlling and testing all device pins. This multi-functionality allows the same physical connections to serve multiple testing and stress application purposes.
2Reliability
If full pin count testing is used to stress all pins, then electrical stress coverage is improved, but test throughput decreases
Solution Approach 1:
The I/O control circuit serves as a mediator that allows full pin control and stress application without requiring full pin count physical connections to the tester. The driver section can selectively drive any pin while the sense section can read from any pin, enabling comprehensive stress testing through a reduced connection interface.
Solution Approach 2:
The testing function is segmented into separate driver and sense sections within the I/O control circuit. The driver section handles stress application to pins while the sense section handles data reading, allowing these functions to be independently optimized and executed through reduced pin count connections.
3Productivity
If split testing (combination of RPC and FPC) is used to improve throughput, then test cost is reduced, but not all device pins are electrically stressed
Solution Approach 1:
The I/O control circuit provides universal control and sensing capability for all pins through a reduced connection set. The driver section can drive any pin and the sense section can read from any pin, making the reduced connection interface universally applicable for both throughput optimization and comprehensive stress testing, eliminating the need for split testing approaches.
Data Source
AI summary
An I/O control circuit includes a plurality of IO cells including an input section for stimulating a plurality of (n) pins of a device under test (DUT) and an output section for processing data output by the pins. The input section of each cell includes a latched driver each including a driver input, a first driver output, a next state driver output, and a current source. The next state driver output and current source are for coupling to drive the pins, and the latched drivers are serially connected with the first driver output of an earlier IO cell connected to the driver input of a next IO cell. The output section of each cell includes an analog to digital converter (ADC) for coupling to the n pins, and a memory element coupled to an output of the ADC.