IO Driver Contactless Test Using On-Chip Voltage Comparison
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Solution Overview
Problem
The use of chip probe pads for chip testing significantly increases capacitance load, limiting IO speed and negatively affecting performance, especially in high-speed operations.
Innovation Solution
A chip and method for performing a contactless chip test using an IO driver, receiver, and processor, which includes a reference voltage generator and comparator to determine test results without external ATE, utilizing a micro-bump pad with reduced capacitance load.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If chip probe pad is used to contact with ATE for chip testing, then test coverage is enhanced, but capacitance load on chip increases significantly
Solution Approach 1:
The patent extracts the testing function from external ATE equipment and relocates it to on-chip components (receiver, reference voltage generator, comparator). This eliminates the need for chip probe pads to contact external ATE, thereby removing the source of excessive capacitance load while preserving test coverage through integrated self-testing capability
Solution Approach 2:
The chip performs its own testing using integrated components (IO driver, receiver, reference voltage generator, comparator) without requiring external ATE equipment. The chip self-evaluates its IO driver performance by generating test signals internally and comparing them against reference voltages, achieving self-service testing that avoids external capacitance loading
2Ease of operation
If chip probe pad is used for contact testing, then test access is achieved, but IO speed and performance are limited
Solution Approach 1:
The patent replaces the mechanical contact-based testing system (chip probe pads physically contacting ATE) with an electrical field-based self-testing system. The IO driver generates test signals that are received and compared electronically within the chip, eliminating mechanical contact and its associated capacitance effects that limit IO speed
Solution Approach 2:
The patent introduces an intermediary on-chip receiver and comparator system that mediates between the IO driver output and the test evaluation function. This intermediary enables test access without requiring external physical contact, allowing high-speed IO operations to proceed unaffected by external probe pad capacitance
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances IO operating speed and performance by eliminating the need for chip probe pads, preventing capacitance load increase, and avoiding additional costs, thus maintaining performance without side effects.
Implementation Method 1
The reference voltage generator is configured to provide a reference voltage
Implementation Method 2
the comparator is configured to compare the IO voltage with the reference voltage in order to generate a comparison result
Data Source
AI summary
A chip for performing a contactless chip test and a method for performing the contactless chip test on an input/output (IO) driver are provided. The chip includes the IO driver, a receiver and a processor, wherein the IO driver and the receiver are coupled to an IO pad, and the processor is coupled to the IO driver and the receiver. The IO driver drives an IO voltage on the IO pad, and the receiver receives the IO voltage from the IO pad, wherein the receiver includes a reference voltage generator and a comparator, the comparator is coupled to the reference voltage generator. The reference voltage generator provides a reference voltage, and the comparator compares the IO voltage with the reference voltage in order to generate a comparison result. The processor determines whether the IO driver passes the contactless chip test according to the comparison result.