I/O Interface Circuit for Integrated Circuit Test Coverage

Resolve Bottlenecks,
Find Innovative Solutions
Generate Solutions

Solution Overview

Problem

Traditional scan chain testing methods are inadequate in fully detecting all areas of integrated circuits, particularly combinational logics directly connected to I/O interfaces, due to limitations in test coverage and the inability to effectively test internal circuits of I/O interfaces.

Innovation Solution

A circuit testing system comprising a control circuit and an I/O interface circuit that receives a scan control signal to propagate scan test signals and response signals between a test machine and a circuit under test, enhancing detection coverage by eliminating the need for scan wrappers and allowing direct signal transmission during the capture mode.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If traditional scan chain testing methods are used, then the testing process is simple, but the test coverage is insufficient and cannot detect all areas of the integrated circuit

Engineering Contradiction:
Improvetest coverageVSAvoidtesting system complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The I/O interface circuit is designed to perform multiple functions: it serves as both the normal input/output interface for circuit operation and as a test signal transmission path. During test mode, the same I/O interface circuit conducts scan test signals to the scan chain circuit and conducts response signals from the circuit under test to the test machine, eliminating the need for separate dedicated test interfaces and achieving full circuit coverage including combinational logics and I/O interface internal circuits

Inventive Principle:
Principle #6Universality (Multi-functionality)

2Reliability

If scan wrappers are added to test combinational logics, then test coverage increases, but the circuit complexity increases and some interfaces still cannot be fully tested

Engineering Contradiction:
Improvetest coverageVSAvoidcircuit complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The invention extracts the test function from the traditional scan chain structure and integrates it into the existing I/O interface circuit. By removing the need for separate scan wrappers and utilizing the I/O interface circuit's existing structure for test signal transmission, the solution achieves comprehensive test coverage of combinational logics and I/O interface internal circuits without adding extra wrapper circuits, thereby reducing overall circuit complexity while maintaining high test coverage

Inventive Principle:
Principle #2Taking out (Extraction)

3Productivity

If the I/O interface circuit conducts scan chain circuit during test mode, then scan patterns can be transmitted, but the circuit under test cannot be directly tested

Engineering Contradiction:
Improvesignal transmission efficiencyVSAvoidcircuit detection accuracy
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The I/O interface circuit is designed with dynamic switching capability controlled by the scan control signal. When the scan control signal is at the first level, the I/O interface circuit conducts the scan chain circuit to receive scan patterns from the test machine. When the scan control signal is at the second level, the I/O interface circuit conducts the circuit under test to the test machine to propagate response signals. This dynamic reconfiguration allows the same circuit structure to serve different test objectives at different times, achieving both efficient signal transmission and accurate circuit detection

Inventive Principle:
Principle #15Dynamics

Data Source

PatentUS11061073B2Circuit testing system and circuit testing method
Publication Date: 2021.07.13 REALTEK SEMICON CORP
  • US11061073B2 patent drawing
  • US11061073B2 patent drawing
  • US11061073B2 patent drawing

AI summary

The present disclosure relates to a circuit testing system, including a control circuit and an interface circuit. The control circuit is electrically connected to a test machine, and configured to receive a scan control signal. The I/O interface circuit is electrically connected to the control circuit, the test machine, the scan chain circuit and a circuit under test. When the scan control signal is at a first level, the control circuit is configured to control the I/O interface circuit to conduct the scan chain circuit to the test machine. When the scan control signal is at a second level, the control circuit is configured to control the I/O interface circuit to conduct the circuit under test to the test machine so as to propagate a response signal generated by the circuit under test to the test machine.