General Purpose I/O Interface for Test Debug Trace Data Exchange
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Solution Overview
Problem
Current systems for debugging and tracing in electronic devices, such as laptops and smartphones, rely on dedicated interfaces and ports, which are inefficient and not scalable, especially in 'closed chassis' designs that aim to minimize external connectors, leading to a need for a more unified and high-speed method to facilitate debug, test, and trace operations across multiple components.
Innovation Solution
Adapting general-purpose input/output interfaces like PCIe and Thunderbolt to support debug, test, and trace functionality, allowing a single external interface to access an internal network of test access points and enable communication between multiple system components, thereby eliminating the need for dedicated debug ports and increasing data transfer rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If dedicated debug ports and interfaces are used for test and trace operations, then debug and trace functionality is supported, but the number of external connectors increases and data transfer rates are limited
Solution Approach 1:
The patent applies universality by enabling a general-purpose external interface to perform multiple functions: it can transmit both operational data and test/debug/trace information. The interface is configured to support different communication modes (operational mode and test mode), allowing a single connector to replace what would traditionally require separate dedicated debug ports and high-speed trace ports.
2Adaptability or versatility
If multiple dedicated interfaces are used for operational data and test information, then both functions are supported, but device complexity increases
Solution Approach 1:
The patent merges the functionality of separate operational data transmission and test information transmission into a single external interface. The interface can be configured to operate in different modes: transmitting operational data during normal operation, and transmitting test/debug/trace information when needed. This combining approach maintains full functional capability while reducing the number of physical connectors and simplifying the interface configuration.
3Speed
If high-speed dedicated trace ports are used, then trace data rate requirements are met, but closed chassis designs with fewer connectors cannot be achieved
Solution Approach 1:
The patent applies dynamics by making the external interface configurable and adaptable. The interface can dynamically switch between operational mode (for normal data transmission) and test mode (for debug/trace operations). The communication parameters such as data rate, packet format, and protocol can be adjusted based on the current operational state, allowing the same physical interface to meet high-speed trace requirements without requiring a dedicated high-speed connector.
Data Source
AI summary
Techniques and mechanisms to exchange test, debug or trace (TDT) information via a general purpose input/output (I/O) interface. In an embodiment, an I/O interface of a device is coupled to an external TDT unit, wherein the I/O interface is compatible with an interconnect standard that supports communication of data other than any test information, debug information or trace information. One or more circuit components reside on the device or are otherwise coupled to the external TDT unit via the I/O interface. Information exchanged via the I/O interface is generated by, or results in, the performance of one or more TDT operations to evaluate the one or more circuit components. In another embodiment, the glue logic of the device interfaces the I/O interface with a test access point that is coupled between the one or more circuit components and the I/O interface.