High-Speed I/O Margin Tester for Multi-Lane Links
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Solution Overview
Problem
Traditional Bit Error Rate Testers (BERTs) and oscilloscopes are costly, complex, and difficult to use for high-speed I/O testing, especially for multi-lane links, leading to infrequent use in pre-production and production testing, which can miss subtle issues affecting the performance of high-speed electrical links like PCI Express.
Innovation Solution
A high-speed I/O margin tester system that assesses multi-lane links in both transmit and receive directions, using a field programmable gate array (FPGA) controller to inject controlled noise and jitter, allowing for simultaneous testing of all lanes and providing easy-to-use, cost-effective solutions for identifying electrical margin issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional BERTs and oscilloscopes are used for high-speed I/O testing, then measurement precision is improved, but device complexity and cost increase significantly
Solution Approach 1:
The patent segments the testing function by implementing lane-by-lane testing of multi-lane I/O links. Each lane can be tested independently through the test fixture, allowing the complex multi-lane signal to be broken down into simpler single-lane measurements that can be performed with more straightforward test equipment and procedures.
Solution Approach 2:
The patent introduces a test fixture as an intermediary component between the device under test and the testing equipment. This fixture includes test points and signal routing that simplify the measurement process by providing controlled access to each lane's signal, making the testing process more manageable and less complex while maintaining measurement accuracy.
2Measurement precision
If traditional testing methods are used, then measurement precision is improved, but ease of operation deteriorates
Solution Approach 1:
By segmenting the multi-lane I/O link into individual lanes for separate testing, the patent simplifies the operation process. Each lane can be tested independently with standardized procedures, making the overall testing process more straightforward and easier to operate compared to attempting to measure all lanes simultaneously with complex equipment.
Solution Approach 2:
The test fixture is designed to automatically identify and test each lane through the multi-lane link without requiring manual configuration or complex setup by the operator. The fixture self-configures the test points and signal routing for each lane, making the testing process more user-friendly and easier to operate.
3Measurement precision
If traditional BERTs and oscilloscopes are used, then measurement precision is improved, but productivity deteriorates due to infrequent use
Solution Approach 1:
The patent enables parallel testing of multiple lanes by segmenting the testing process into independent lane-level measurements. This allows multiple lanes to be tested simultaneously or in rapid succession using the same test fixture, significantly increasing testing throughput and productivity compared to sequential testing with traditional equipment.
Solution Approach 2:
The test fixture is designed with universal applicability to test all lanes of the multi-lane I/O link using the same hardware platform. This multi-functional capability allows a single fixture to handle various lane configurations and testing scenarios, improving productivity by eliminating the need for multiple specialized test setups and enabling faster, more frequent testing.
4Measurement precision
If traditional testing equipment is used, then measurement precision is improved, but ease of manufacture deteriorates
Solution Approach 1:
The patent simplifies the manufacturing and implementation process by segmenting the test fixture into modular components that can be independently manufactured and assembled. Each lane testing function is implemented as a separate, standardized module within the fixture, making the overall system easier to manufacture and implement compared to building a complete multi-lane testing system from scratch using traditional equipment.
Data Source
AI summary
Systems, devices and methods for high-speed I/O margin testing can screen high volumes of pre-production and production parts and identify cases where the electrical characteristics have changed enough to impact operation. The margin tester disclosed is lower cost, easier to use and faster than traditional BERT and scopes and can operate on the full multi-lane I/O links in their standard operating states with full loading and cross-talk. The margin tester assesses the electrical receiver margin of an operation multi-lane high speed I/O link of a device under test simultaneously in either or both directions. In a technology-specific form, an embodiment of the margin tester can be implemented as an add-in card margin tester to test motherboard slots of a mother board under test, or as a as a motherboard with slots to test add-in cards.