Multi-Channel I/O Switching Layout for SSO Noise Mitigation
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Solution Overview
Problem
Simultaneous switching output (SSO) noise in multi-channel devices, such as SoC controllers and solid state drives, causes voltage drops and instability due to high instantaneous current changes, leading to signal integrity and power integrity issues, especially in high-speed parallel buses.
Innovation Solution
The method involves calculating worst-case scenario currents and channel skews to determine optimal switching currents and delays, grouping channels, and using signal integrity-power integrity simulations to reduce SSO noise by spreading channel switching over a bit period, thereby minimizing peak switching power and current consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If multiple I/O channels switch simultaneously to increase data throughput, then productivity is improved, but simultaneous switching output noise increases causing voltage drops and signal integrity issues
Solution Approach 1:
The patent divides the simultaneous switching of multiple I/O channels into segmented time slots within a bit period. Channels are grouped and assigned specific time slots for switching, spreading the switching events across the entire bit period rather than occurring simultaneously. This segmentation reduces peak current demand and mitigates SSO noise while maintaining overall data throughput.
Solution Approach 2:
The patent implements periodic switching patterns where channels switch at regular intervals determined by calculated delays. The switching is organized in a periodic manner across multiple time slots, with each channel having a predetermined switching time based on its group assignment. This periodic distribution of switching events reduces simultaneous current draws and associated noise.
2Reliability
If channel switching is spread over a bit period to reduce SSO noise, then signal integrity is improved, but channel skew increases affecting timing precision
Solution Approach 1:
The patent calculates and applies specific delay parameters to each channel group to optimize the balance between SSO noise reduction and timing precision. The delay values are determined based on worst-case skew calculations and are adjusted to ensure that channels within each group switch at appropriate intervals. This parameter optimization allows spreading switching events to reduce noise while maintaining acceptable timing precision through careful delay calibration.
3Use of energy by moving object
If channels are grouped with longer delays to reduce switching current, then power consumption is reduced, but bandwidth utilization decreases
Solution Approach 1:
The patent applies partial action by spreading channel switching across the entire bit period rather than concentrating it in a single instant. By distributing switching events throughout the available time window, the patent reduces peak current demand without completely eliminating switching activity within each bit period. This partial spreading approach achieves current reduction while maintaining adequate bandwidth utilization.
Data Source
AI summary
Method of reducing simultaneous switching output (SSO) impact in a system through the use of signal integrity/power integrity (SI/PI) simulations for each channel in the system includes calculating a worst case scenario current for a channel of the system, and calculating a worst case channel skew for a channel of the system. Based on the worst case scenario current and the worst case channel skew, a switching current is determined for the system.