Integrated Passive Die Layouts Through Wafer Dicing
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Solution Overview
Problem
Conventional integrated passive device (IPD) dies have fixed sizes and electrical properties, limiting circuit design flexibility and fabrication options.
Innovation Solution
The development of integrated passive device dies with varying sizes and numbers, achieved by dicing semiconductor wafers to create a plurality of IPD dies with customizable configurations, allowing for greater design flexibility and fabrication options.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If conventional integrated passive device dies are used with fixed sizes and electrical properties, then manufacturing simplicity is maintained, but circuit design flexibility is limited
Solution Approach 1:
The patent divides a semiconductor wafer into multiple separate IPD dies of different sizes by dicing along scribe lines. This segmentation allows the wafer to be customized into various configurations (e.g., single die, dual die, quad die) while maintaining standardized manufacturing processes for the entire wafer, thus resolving the contradiction between design flexibility and fabrication complexity.
Solution Approach 2:
The patent creates a universal wafer platform that can produce multiple types of IPD dies with different sizes and configurations using the same fabrication process. The wafer-level manufacturing maintains universality and simplicity, while the post-fabrication dicing provides customization, allowing one manufacturing system to serve multiple design needs.
2Adaptability or versatility
If IPD dies are customized with varying sizes and numbers, then design flexibility is enhanced, but manufacturing complexity increases
Solution Approach 1:
The patent performs all fabrication processes at the wafer level before dicing, including forming IPD devices, depositing interconnect structures, and creating bonding pads. This preliminary action allows standardized manufacturing to create fully functional IPD devices on the entire wafer, and customization is achieved later through simple dicing operations, thus maintaining ease of manufacture while enabling configuration customization.
3Quantity of substance
If fixed-size IPD dies are manufactured, then manufacturing simplicity is maintained, but integration density is limited
Solution Approach 1:
The patent segments the wafer into different数量的IPD dies (single, dual, quad configurations) by controlling the dicing pattern. This allows optimization of integration density for different applications - for example, cutting the wafer into four smaller dies increases the number of components per unit area, while maintaining the same fabrication process complexity.
Data Source
AI summary
A method of fabricating integrated passive device dies includes forming a first plurality of integrated passive devices on a substrate, forming a plurality of micro-bumps on the first plurality of integrated passive devices such that the plurality of micro-bumps act as electrical connections to the integrated passive devices, and dicing the substrate to form an integrated passive device die including a second plurality of integrated passive devices. The micro-bumps may be formed in an array or staggered configuration and may have a pitch that is in a range from 20 microns to 100 microns. The integrated passive devices may each include a seal ring and the integrated passive device die may have an area that is a multiple of an integrated passive device area. The method may further include dicing the substrate in various ways to generate integrated passive device dies having different sizes and numbers of integrated passive devices.