Integrated Passive Device on Glass Substrate for Compact PDN
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Solution Overview
Problem
Conventional decoupling capacitors in Power Delivery Networks (PDNs) are space-intensive and require complex board designs, leading to a need for a more compact and simplified design for integrated passive devices (IPDs) that can effectively minimize noise and resonance interference.
Innovation Solution
A semiconductor device with a substrate featuring a cavity occupied by interconnect material, such as solder balls, and integrated passive devices (IPDs) like capacitors, inductors, or resistors, coupled to metal layers, which are configured to be electrically connected when coupled to an integrated circuit (IC), enabling high-density IPD integration.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of stationary object
If conventional decoupling capacitors are used on PCB, then power delivery network functionality is provided, but real estate space is excessive and board design becomes complicated
Solution Approach 1:
The patent merges the decoupling capacitor with the substrate by forming the capacitor structures directly on the substrate surface. The first and second conductive layers are deposited on the substrate, with the dielectric layer between them, creating an integrated capacitor-substrate assembly that eliminates the need for separate discrete capacitors and reduces board space requirements.
Solution Approach 2:
The patent transitions from planar PCB mounting to three-dimensional capacitor structures on the substrate. By stacking conductive and dielectric layers vertically on the substrate surface, the design utilizes the vertical dimension to achieve higher capacitance density without increasing the horizontal footprint, thereby reducing real estate space consumption.
2Object-affected harmful factors
If decoupling capacitors are integrated closer to IC/die, then noise and resonance interference is reduced, but manufacturing complexity increases
Solution Approach 1:
The patent segments the capacitor into multiple functional layers (first conductive layer, dielectric layer, second conductive layer) that can be manufactured using standard semiconductor deposition and patterning processes. This segmentation allows each layer to be formed independently using existing manufacturing techniques, reducing overall manufacturing complexity while achieving integrated capacitor functionality.
Solution Approach 2:
The substrate serves multiple functions: it acts as both the mechanical support structure and the base for forming the decoupling capacitor. The same substrate that provides structural support also hosts the capacitor structures, eliminating the need for separate capacitor components and simplifying the manufacturing process by reducing the number of assembly steps.
3Productivity
If high density IPD integration is achieved, then space efficiency is improved, but electrical coupling complexity increases
Solution Approach 1:
The patent implements a nested structure where the dielectric layer is positioned between the first and second conductive layers, with the entire capacitor structure integrated on the substrate. The interconnect material is nested within cavities in the substrate, creating a compact, multi-level electrical coupling architecture that achieves high density while maintaining simple connection paths through vertical alignment.
Data Source
AI summary
Some novel features pertain to a semiconductor device that includes a substrate, a first cavity that traverses the substrate. The first cavity is configured to be occupied by a interconnect material (e.g., solder ball). The substrate also includes a first metal layer coupled to a first side wall of the first cavity. The substrate further includes a first integrated passive device (IPD) on a first surface of the substrate, the first IPD coupled to the first metal layer. In some implementations, the substrate is a glass substrate. In some implementations, the first IPD is one of at least a capacitor, an inductor and/or a resistor. In some implementations, the semiconductor device further includes a second integrated passive device (IPD) on a second surface of the substrate. The second IPD is coupled to the first metal layer.