IPD Polarity Group Layout for Lower ESL and ESR
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Solution Overview
Problem
The semiconductor industry faces challenges in reducing equivalent series inductance (ESL) and equivalent series resistance (ESR) in integrated passive devices (IPDs), which limits operating frequency and efficiency, respectively, due to the shrinking size of semiconductor devices and increasing parasitic characteristics.
Innovation Solution
The implementation of an integrated passive device (IPD) with conductive bumps forming three or more polarity groups and large vias in the topmost via layer, reducing ESL and ESR by optimizing the shape and area ratio of conductive bumps and vias, respectively.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Area of moving object
If the size of semiconductor devices is reduced to increase integration density, then more components can be integrated into a given area, but parasitic characteristics (ESL and ESR) increase, limiting operating frequency and efficiency
Solution Approach 1:
The patent divides the conductive bump structure into multiple polarity groups (first polarity group, second polarity group, third polarity group) with different configurations. Each polarity group is segmented into multiple regions (first region, second region, third region) with varying via sizes and conductive bump arrangements. This segmentation allows independent optimization of each segment to reduce overall parasitic characteristics while maintaining high integration density.
Solution Approach 2:
The patent applies local quality by making different parts of the conductive bump structure have different properties. Specifically, the topmost via layer has larger via size in certain regions to reduce ESL, while lower via layers have smaller via sizes. The conductive bumps in different polarity groups have different geometries and arrangements tailored to their specific electrical requirements, optimizing local electrical characteristics to reduce parasitic effects.
2Speed
If larger vias are formed in the topmost via layer to reduce ESL, then operating frequency increases, but processing time and manufacturing complexity increase
Solution Approach 1:
The via structure is segmented into multiple layers with different via sizes. The topmost via layer uses larger via sizes optimized for ESL reduction and high-frequency operation, while lower via layers use smaller via sizes that are easier and faster to manufacture. This segmentation allows the system to achieve high operating frequency without requiring all vias throughout the structure to be large, thereby reducing overall processing time and manufacturing complexity.
Solution Approach 2:
The patent resolves the contradiction by transitioning from a uniform via size approach to a multi-layered via size approach. Instead of making all vias large throughout the entire interconnect structure, the solution uses different via sizes in different vertical layers (dimensions), optimizing each layer's via size for its specific function. This dimensional differentiation allows ESL reduction at the top layer while maintaining manufacturing efficiency in lower layers.
3Reliability
If multiple polarity groups with optimized configurations are implemented to reduce ESR and ESL, then device performance improves, but device complexity increases
Solution Approach 1:
The conductive bump structure is segmented into multiple polarity groups (first, second, and third polarity groups) with distinct configurations. Each polarity group contains conductive bumps in different regions with specific geometries and via structures optimized for their electrical function. This segmentation enables independent optimization of each polarity group to reduce ESR and ESL while maintaining overall structural organization and manageability.
Solution Approach 2:
The patent implements multi-functionality by designing the conductive bump structure to simultaneously achieve multiple objectives: reducing ESL through larger topmost vias, reducing ESR through optimized conductive bump configurations, maintaining high integration density, and enabling high operating frequency. The same segmented polarity group structure serves all these functions concurrently, improving device performance without proportionally increasing complexity.
Data Source
AI summary
A semiconductor device includes passive electrical components in a substrate; and an interconnect structure over the passive electrical components, conductive features of the interconnect structure being electrically coupled to the passive electrical components. The conductive features of the interconnect structure includes a first conductive line over the substrate; a conductive bump over the first conductive line, where in a plan view, the conductive bumps has a first elongated shape and is entirely disposed within boundaries of the first conductive line; and a first via between the first conductive line and the conductive bump, the first via electrically connected to the first conductive line and the conductive bump, where in the plan view, the first via has a second elongated shape and is entirely disposed within boundaries of the conductive bump.