I/Q LO Circuit With Feedback-Stabilized Non-Overlapping Phases
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Solution Overview
Problem
Conventional local oscillator signals in RF receivers suffer from 1/f-noise, leading to fluctuations in duty cycle and pulse position, which result in 1/f-noise pollution at the IF output, especially in zero-IF or near-zero-IF receivers due to the use of MOS transistors in CMOS frequency dividers.
Innovation Solution
A circuit arrangement comprising a break-before-make circuit, detectors for measuring duty cycle, differential amplifiers to determine and adjust duty cycle differences, and buffers to ensure non-overlapping signals with constant and equal duty cycles, along with a feedback loop to maintain fixed relative positions, reduces 1/f-noise by adjusting logic thresholds and using NAND-gates for well-defined delays.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If MOS transistors are used in CMOS frequency dividers to generate local oscillator signals, then the device complexity is reduced and integration is improved, but 1/f-noise is introduced causing duty cycle and pulse position fluctuations
Solution Approach 1:
The patent implements feedback loops that detect duty cycle variations and pulse position shifts caused by 1/f-noise, then generate correction signals to compensate for these variations. The feedback mechanism continuously monitors the LO signal characteristics and adjusts the frequency divider output to maintain constant duty cycle and stable pulse position, thereby eliminating the harmful effects of MOS transistor 1/f-noise while preserving the integrated CMOS structure.
Solution Approach 2:
The patent dynamically adjusts critical parameters of the frequency divider operation, including switching thresholds, bias currents, and timing delays, to compensate for 1/f-noise induced variations. By changing these parameters in real-time based on detected signal quality, the system maintains optimal performance despite the inherent noise characteristics of MOS transistors, resolving the contradiction between using simple CMOS devices and achieving low-noise operation.
2Ease of operation
If duty cycle fluctuations occur in differential I/Q LO signals, then the LO signal generation becomes simpler, but 1/f-noise pollution appears at the IF output due to self-mixing
Solution Approach 1:
The patent employs feedback mechanisms that monitor the duty cycle of differential I/Q LO signals and generate correction signals to maintain constant duty cycle. By detecting variations in real-time and applying compensating adjustments, the system prevents duty cycle fluctuations from causing self-mixing noise at the IF output, thereby maintaining simple LO signal generation while eliminating the harmful noise effect.
Solution Approach 2:
The patent applies preliminary corrections to the LO signals before they reach the mixers, preventing the formation of harmful 1/f-noise components. By pre-compensating for potential duty cycle variations and pulse position shifts through feedback-adjusted timing and threshold control, the system stops the noise generation process before it can pollute the IF output, rather than attempting to filter it afterward.
Data Source
AI summary
The present invention relates to a circuit arrangement (300) for generating non-overlapping and immune-to-1/f-noise signals as has been described. A break-before-make (BBM) circuit ensures that the differential I/Q signals (LO—0, LO—90, LO—180, LO—270), driving the transistors (M11, M12, M21, M22) of mixers (16A, 16B) in an RF receiver (200), are non-over-lapping for having at any time only one of these transistors turned on. The duty cycle of each driving signal is measured, and the difference (Δ) in the duty cycle corresponding to two subsequent LO phases is determined through a respective differential amplifier (38A-38D). Each differential amplifier is configured to have a current output (LT—0, LT—90, LT—180, LT—270), which is then fed back to the input of the input buffer (30A-30D) corresponding to the first LO phase in order to adjust its logic threshold (LT) level and make the difference (Δ) equal to zero. Thereby, the combined action of the BBM circuit and the feedback loops results in four non-overlapping differential I/Q signals (LO—0, LO—90, LO—180, LO—270) with constant and mutually equal duty cycles, and fixed and well-defined relative positions.