Synchronized I/Q Detection Circuit for Faster, Accurate Phase Sampling
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Solution Overview
Problem
Conventional I/Q phase detection circuits face challenges with slow detection time and low accuracy due to reliance on low bandwidth resistor-capacitor (RC) filters and process variation issues, leading to incomplete settling and voltage ripple problems.
Innovation Solution
A synchronized I/Q detection circuit is introduced, featuring multiplexers, phase detectors, reset and sampling circuits, and a comparator to cancel incomplete settling and improve power efficiency by quickly turning transmitters and receivers on/off, reducing power consumption and complexity in modem-RFIC package routing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If low bandwidth RC filters are used to extract DC values from phase detector, then filtering performance is improved, but detection time increases and accuracy decreases
Solution Approach 1:
The patent extracts only the necessary signal components (I and Q components at specific phases) using multiplexers to select signals at 0, 90, 180, and 270 degrees, eliminating the need for low bandwidth RC filters. This extraction approach removes the filtering bottleneck while maintaining signal integrity for phase detection.
Solution Approach 2:
The patent performs preliminary signal conditioning and selection before phase detection by using multiplexers to pre-select and condition signals at specific phases. This preliminary action prepares the signals in advance, eliminating the need for slow post-detection filtering and enabling faster detection.
2Device complexity
If conventional phase detection circuits are used, then implementation is simple, but accuracy is low due to process variation and incomplete settling
Solution Approach 1:
The patent creates a copied and inverted version of the phase detection path by detecting both the original phase relationship and its inverse. This dual-path copying approach allows cancellation of process variations and incomplete settling effects, significantly improving measurement precision while maintaining reasonable circuit complexity.
Solution Approach 2:
The patent implements feedback by comparing the detected phase difference with expected values and using this information to adjust subsequent measurements. The reset and sampling circuits provide feedback control to ensure accurate phase detection despite process variations.
3Measurement precision
If transmitters and receivers remain continuously on, then detection accuracy is maintained, but power consumption increases
Solution Approach 1:
The patent uses periodic action by implementing synchronized sampling that occurs only at specific phases (0, 90, 180, 270 degrees) rather than continuously. The reset and sampling circuits enable periodic measurement cycles, maintaining detection accuracy while allowing the system to enter low-power states between measurements, thus reducing overall power consumption.
Data Source
AI summary
A synchronized I/Q detection circuit is provided. A first subset of input signals and, subsequently, a second subset of input signals are provided by a first multiplexer and received by a first phase detector. Outputs of the first phase detector are receiving, by a first reset and sampling circuit. A second set of input signals are provided by a second multiplexer and received by a second phase detector, from a second multiplexer, while the first multiplexer receives the first and second subsets of input signals. The first subset of input signals has a same phase order as the second set of input signals, and the second subset of input signals has a different phase order than the second set of input signals. Outputs of the second phase detector are received by a second reset and sampling circuit. A comparator outputs a detected phase difference based on the outputs of the first and second reset and sampling circuits.