I/Q Frequency Synthesizer Using PLL Post-Scaling
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Solution Overview
Problem
Conventional frequency synthesizers face performance and cost efficiency degradation at low reference frequencies, requiring complex modifications to generate programmable clock signals over a wide bandwidth, especially for in-phase and quadrature-phase signals, due to issues with phase-locked loops and increased power consumption.
Innovation Solution
A programmable frequency synthesizer design that uses a post-scaler instead of a prescaler, with a digital frequency divider comprising two sub-dividing stages and a duty cycle equalizer to generate in-phase and quadrature-phase clock signals without frequency doubling, allowing efficient operation over a wide range of frequencies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If a phase-locked loop is used to generate clock signals at low reference frequencies, then the frequency synthesizer can operate at low frequencies, but the charge-pump current becomes too small increasing implementation difficulty and the loop filter requires large capacitors increasing chip area or additional on-board components
Solution Approach 1:
Instead of using a prescaler before the PLL as in conventional designs, this patent inverts the approach by using a post-scaler after the PLL. The PLL operates at a high fixed frequency (e.g., 26 MHz reference) where charge-pump current is sufficient and implementation is easy, then a digital post-scaler divides the frequency down to the desired lower output frequencies. This inversion resolves the contradiction by avoiding the small current problem at low frequencies while achieving the same adaptability.
Solution Approach 2:
The patent introduces a digital post-scaler as an intermediary component between the PLL and the output. This post-scaler acts as a mediator that takes the high-frequency PLL output and divides it down to the required lower frequencies, thereby enabling low-frequency operation without subjecting the PLL itself to low-frequency challenges. The intermediary resolves the contradiction by decoupling the PLL operating conditions from the final output frequency requirements.
2Adaptability or versatility
If a loop filter with narrow bandwidth is used to achieve low cutoff frequency, then the frequency synthesizer can operate at low frequencies, but the settling time becomes very long
Solution Approach 1:
The patent inverts the conventional approach by maintaining a fixed high-frequency PLL with an optimized loop filter bandwidth for fast settling, then using a post-scaler to achieve the desired low output frequencies. This resolves the contradiction because the PLL operates at high frequency where a wider bandwidth can be used, resulting in fast settling times, while the post-scaler provides the low cutoff frequency effect at the output without the long settling time penalty.
3Adaptability or versatility
If frequency doubling is used to generate quadrature-phase signals, then both in-phase and quadrature-phase clock signals can be generated, but the design complexity and power consumption increase
Solution Approach 1:
The patent extracts the frequency doubling function from the signal generation path and replaces it with a dedicated digital divide-by-two counter that directly generates quadrature-phase outputs from the PLL clock. By taking out the complex frequency doubling circuitry (XOR gates or VCO-based doubling) and replacing it with a simple digital counter that naturally produces quadrature outputs, the design complexity is reduced while maintaining I/Q signal generation capability.
Solution Approach 2:
The patent substitutes the analog/mixed-signal frequency doubling mechanism (using XOR logic gates or VCO-based doubling) with a digital divide-by-two counter implementation. This mechanical/electrical substitution from analog logic to digital counting simplifies the circuit, reduces power consumption, and eliminates high-frequency glitches while achieving the same quadrature-phase signal generation function.
4Adaptability or versatility
If frequency doubling is used to generate quadrature-phase signals, then both in-phase and quadrature-phase clock signals can be generated, but power consumption increases
Solution Approach 1:
The patent substitutes the power-hungry frequency doubling circuitry (XOR gates or VCO-based doubling) with a low-power digital divide-by-two counter. This substitution dramatically reduces power consumption because digital counters operate at lower frequencies and with simpler logic, eliminating the need for high-frequency switching and complex analog circuitry while still generating the required quadrature-phase signals.
Data Source
AI summary
Various embodiments of the present invention relate to systems, devices and method of frequency synthesis that generate in-phase and quadrature-phase clock signals at a programmable frequency. The generated frequency, which can range from a fraction to multiples of the input reference frequency, is generated by dividers following a phase-locked loop, thus avoiding the use of a low input reference frequency as well as frequency doubling.