Island Semiconductor Memory Cell Array Layout
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Solution Overview
Problem
The challenge in NOR-type flash memory is to inject electric charge into a charge accumulation layer using the FN tunnel current without compromising large-scale integration of memory cells, as conventional designs face issues with short channel effects and increased leakage currents due to the hot electron injection method.
Innovation Solution
A memory cell array is designed with island semiconductor layers serving as source lines, tunnel insulation films, charge accumulation layers on the sidewalls, and control gates, where bit lines and source lines are laid out in columns and rows respectively, allowing for parallel alignment without increasing the memory cell area, enabling efficient FN tunnel current injection and high-speed reading.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If hot electron injection method is used in NOR-type flash memory, then charge can be injected into the charge accumulation layer, but the writing speed is slow and the current required is high
Solution Approach 1:
The patent changes the injection mechanism from hot electron injection to FN tunnel current injection by modifying the voltage application method. By applying voltage perpendicular to the memory cell (control gate voltage) instead of along the source-drain direction, the patent achieves charge injection through quantum tunneling effect, which enables concurrent high-speed writing and high reliability without requiring high current
Solution Approach 2:
The patent replaces the hot electron injection mechanism (which relies on kinetic energy from source-drain voltage) with FN tunnel current injection (which relies on quantum mechanical tunneling through the tunnel oxide film). This substitution eliminates the need for high source-drain voltage and enables faster, lower-current writing operations
2Quantity of substance
If gate length is reduced to increase memory capacity, then integration density improves, but short channel effect increases leakage current
Solution Approach 1:
The patent changes the voltage application parameters from parallel (source-drain voltage for hot electron injection) to perpendicular (control gate voltage for FN tunnel current). This parameter change eliminates the short channel effect's impact on leakage current while enabling continued scaling of gate length to increase memory capacity
Solution Approach 2:
The patent extracts the voltage application from the source-drain path and applies it instead through the control gate. This separation removes the harmful short channel effect from the injection process, allowing gate length reduction for higher capacity without proportionally increasing leakage current
3Adaptability or versatility
If source lines are connected to all memory cells in conventional NOR architecture, then all memory cells can be accessed, but bit lines are short-circuited when high voltage is applied to control gate line
Solution Approach 1:
The patent introduces a transistor as an intermediary between the source line and the memory cell source diffusion layer. This transistor acts as a switch that can be controlled to connect or disconnect the source line, preventing bit line short-circuiting while maintaining the ability to access all memory cells when needed
Solution Approach 2:
The patent makes the source line connection dynamic by using transistors that can be turned on or off based on the operation being performed. During FN tunnel current injection, the transistor is off to prevent short-circuiting; during reading or other operations, it can be on to enable access. This dynamic control resolves the contradiction between universal accessibility and conduction stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration allows for high-speed and reliable writing and reading by isolating source and bit lines, reducing resistance, and enabling efficient FN tunnel current injection, thus overcoming the limitations of conventional NOR-type flash memory designs.
Implementation Method 1
injection of electric charge into the charge accumulation layer through the use of an FN (Fowler-Nordheim) tunnel current
Data Source
Figure 1~2
Figure 3~4
Figure 5
AI summary
A memory cell array in a nonvolatile memory is disclosed comprising island semiconductor layers (101) on a substrate (1), wherein the lower parts of the island semiconductor layers (101) serve as source lines (2; SLx) for the memory cells and transistors arranged in a column; a tunnel insulation film (102) on the island semiconductor layers (101); charge accumulation layers (6) on the sidewalls of the island semiconductor layers (101); an insulating film (104) on the charge accumulation layers (6); control gates (7) of the memory cells and read lines (11) of transistors arranged in a row on the insulating film (104); source diffusion layers (3, 8) and drain diffusion layers (5, 10) in the island semiconductor layers (101); and common source lines (12; CSL) for the transistors arranged in a row and first bit line parts (13) for the memory cells, and second bit line parts (15) for the memory cells, wherein the first and second bit line parts (13, 15) for the memory cells are laid out in columns and the common source lines (12; CSL) for the transistors are laid out in rows.