Self-Aligned Islanding Gate Structures for NAND Memory
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Solution Overview
Problem
The miniaturization of semiconductor technology has made it increasingly difficult to precisely control the line width and spacing of word lines in NAND memory cell arrays, leading to issues with misalignment and unsuccessful patterning in the manufacturing of NAND memory cells.
Innovation Solution
A method for manufacturing NAND memory cells that involves forming self-aligned islanding gate structures using a substrate with shallow trench isolation (STI), where a conductive layer serves as the control-gate or select gate, eliminating the need for high-grade photomasks and alignment processes, and improving the gate coupling ratio with conductive spacers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional photomask alignment processes are used to define control gates, then patterning can be achieved, but misalignment and unsuccessful patterning occur due to miniaturization challenges
Solution Approach 1:
The control gate is formed through a self-aligned process where the gate material is deposited conformally on the trench structure and then planarized. This self-alignment mechanism eliminates the need for separate photomask alignment steps, allowing the control gate to automatically position itself relative to the trench with high precision, thereby resolving the misalignment issues caused by miniaturization
Solution Approach 2:
The trench structure serves as an intermediary element that defines the position of the control gate. By forming the control gate within the trench through conformal deposition and planarization, the trench acts as a physical template that ensures precise positioning without requiring additional alignment processes
2Manufacturing precision
If high-grade photomasks are used for defining control gates, then alignment precision can be improved, but process complexity and manufacturing cost increase
Solution Approach 1:
The self-aligned formation of control gates through conformal deposition and planarization eliminates the need for high-grade photomasks entirely. The process uses the trench structure itself as the alignment reference, simplifying the manufacturing process and reducing equipment requirements while maintaining high precision
Solution Approach 2:
The invention extracts and eliminates the photomask alignment step from the manufacturing process. By using self-aligned conformal deposition, the control gate definition process no longer requires external photomasks, thereby reducing process complexity and manufacturing cost
Data Source
AI summary
A method for manufacturing NAND memory cells includes providing a substrate having a first doped region formed therein; forming a first dielectric layer, a storage layer and a patterned hard mask on the substrate; forming a STI in the substrate through the patterned hard mask and removing the patterned hard mask to define a plurality of recesses; forming a second dielectric layer and a first conductive layer filling the recesses on the substrate; and performing a planarization process to remove a portion of the first conductive layer and the second dielectric layer to form a plurality of self-aligned islanding gate structures.