Isolated Inter-Gate Dielectric Regions in NAND Flash Memory
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As device geometries decrease, interference between adjacent floating gates in NAND flash memory devices becomes a significant issue, affecting the operation of memory cells due to capacitive interference through the inter-gate dielectric layer, especially with high-k materials that reduce tunneling current but increase FG-FG capacitance.
Innovation Solution
The solution involves eliminating the capacitive path between floating gates by using electrically isolated inter-gate dielectric regions instead of a continuous high-k dielectric layer, reducing FG-FG capacitance by creating trenches and depositing inter-gate dielectric layers in a way that they are planarized and isolated from adjacent regions, thereby minimizing interference.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If a continuous high-k dielectric layer is used between floating gates, then tunneling current is reduced, but capacitive interference between adjacent floating gates increases
Solution Approach 1:
The continuous high-k dielectric layer is segmented into isolated regions by introducing trenches between adjacent floating gates. This segmentation breaks the capacitive coupling path while preserving the tunneling barrier function, as each isolated dielectric region maintains its electrical isolation properties locally while eliminating long-range interference.
Solution Approach 2:
The trench structure acts as an intermediary element between adjacent floating gates, physically separating the high-k dielectric regions. This intermediary structure (trench filled with low-k material or void) mediates the interaction between floating gates by providing electrical isolation while allowing the high-k dielectric to maintain its tunneling barrier function.
2Quantity of substance
If device geometries are decreased to increase memory density, then storage capacity is improved, but interference between adjacent floating gates becomes more significant
Solution Approach 1:
By segmenting the dielectric layer into isolated regions through trenches, the patent enables closer spacing of memory cells without increasing interference. Each segmented dielectric region is electrically isolated, allowing device geometries to be decreased while maintaining signal integrity and reducing capacitive coupling between adjacent cells.
Solution Approach 2:
The patent applies different dielectric properties locally: high-k dielectric material is used directly at the floating gate interface to minimize tunneling current, while low-k or void regions are introduced between adjacent floating gates to minimize capacitive interference. This local differentiation of dielectric quality allows simultaneous optimization of both tunneling barrier and interference reduction.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach effectively reduces FG-FG capacitance, improving the operational reliability and performance of NAND flash memory devices by minimizing unwanted interference between adjacent memory cells.
Implementation Method 1
The floating gate is generally formed over the channel and separated from the channel by a gate oxide
Implementation Method 2
interference between adjacent floating gates becomes a significant issue, affecting the operation of memory cells due to capacitive interference through the inter-gate dielectric layer
Data Source
AI summary
A memory array comprising transistors having isolated inter-gate dielectric regions with respect to one another. Transistors are formed such that each of the transistors in the array has a charge storage region such as a floating gate, a control gate and an inter-gate dielectric layer therebetween. The inter-gate dielectric layer for each transistor is isolated from the inter-gate dielectric of each of the other transistors in the array.