Isolated Middle Electrodes for 3D Memory Selectivity
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Solution Overview
Problem
Existing three-dimensional memory devices face challenges in achieving high memory cell density and efficient manufacturing processes, particularly in vertical ReRAM architectures where the integration of non-volatile memory elements and conductive elements is complex, leading to issues with selectivity and operational voltage.
Innovation Solution
A monolithic three-dimensional memory device structure is developed, featuring discrete, isolated middle electrodes between non-volatile memory elements and bit lines, allowing for independent electrode selection and reduced IR drop, along with a method of fabricating ReRAM devices that includes forming a stack of conductive and insulating layers, etching openings, depositing non-volatile memory material, and creating isolated electrodes within recessed portions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If continuous middle electrode layers are used in vertical ReRAM architecture, then manufacturing process is simplified, but memory cell selectivity deteriorates and operational voltage increases due to IR drop
Solution Approach 1:
The continuous middle electrode layer is segmented into discrete isolated middle electrodes positioned at specific word line intersections. This segmentation enables individual electrode control for each memory cell, improving selectivity while maintaining manufacturing feasibility through patterned deposition processes.
Solution Approach 2:
The middle electrodes are positioned locally at specific intersections of bit lines and word lines, with electrodes present only on selected sides of bit line pillars. This local placement optimizes current flow paths for each memory cell, reducing IR drop and improving operational voltage characteristics while maintaining manufacturing simplicity.
2Area of moving object
If higher memory cell density is achieved through vertical stacking, then area efficiency improves, but manufacturing complexity and selectivity control worsen
Solution Approach 1:
The memory architecture transitions from two-dimensional planar arrays to three-dimensional vertical stacking, with multiple word lines stacked vertically and bit lines extending in the vertical direction. This dimensional change increases memory cell density per unit area while the isolated middle electrode structure simplifies the integration process by enabling independent electrode control at each vertical level.
3Reliability
If isolated middle electrodes are implemented, then memory cell selectivity and operational voltage improve, but manufacturing process complexity increases
Solution Approach 1:
The isolated middle electrodes are formed during the initial deposition sequence, with electrode material deposited conformally over the substrate before bit line pillar formation. This preliminary action integrates electrode fabrication into the existing manufacturing flow, avoiding additional processing steps while achieving the selectivity benefits of isolated electrodes.
Data Source
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Figure 3A~3C
AI summary
A monolithic, three-dimensional memory device includes a substrate and a plurality of electrically conductive word lines over a major surface of the substrate. An electrically conductive bit line extends in a direction substantially perpendicular to the major surface of the substrate and adjacent to each of the plurality of word lines, and a non-volatile memory element material is located between the bit line and each of the plurality of word lines. A plurality of middle electrodes comprising an electrically conductive material are located between the bit line and each of the plurality of word lines, wherein the plurality of middle electrodes are discrete electrodes which are isolated from one another in at least the second direction.