Isolation Cells for Monolithic 3D IC Layer Testing
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Solution Overview
Problem
In monolithic 3D integrated circuits (M3D ICs), the bottom layer cannot be tested separately before the top layer is fabricated, making defect isolation and yield enhancement challenging due to the need for interlayer vias (ILVs) that require precise alignment and are subject to mechanical stress, limiting defect screening and integration efficiency.
Innovation Solution
The integration of isolation cells, such as electronic fuses and tri-state flip-flops, allows for controllable electrical connections between layers, enabling separate testing of the bottom layer by bypassing signals from the top layer through a bypass structure using Munkres algorithm for ILV pairing and cost-optimization to minimize area overhead and ensure defect isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If monolithic 3D integration is used to reduce die footprint and improve performance, then integration density and performance are improved, but the bottom layer cannot be tested separately before top layer fabrication making defect isolation difficult
Solution Approach 1:
The patent divides the monolithic 3D IC into functionally independent segments by introducing isolation cells between layers. These isolation cells can be selectively activated to separate the bottom layer from the top layer, allowing independent testing of each layer while maintaining the integrated structure during normal operation.
Solution Approach 2:
The patent introduces isolation cells as intermediary components between the bottom and top layers. These isolation cells act as mediators that can selectively connect or disconnect the layers, enabling defect isolation and separate testing while maintaining the monolithic integration benefits.
2Use of energy by moving object
If TSV-based 3D ICs are used for interlayer interconnection, then shorter interconnects and less power consumption are achieved, but keep-out-zone leads to significant area overhead
Solution Approach 1:
The patent changes the physical parameters of vertical interconnects by replacing large-diameter TSVs with much smaller ILVs (one to two orders of magnitude smaller). This parameter change reduces the area occupied by interconnects while maintaining the electrical connection benefits.
Solution Approach 2:
The patent transitions from TSV-based 3D integration to monolithic 3D integration, representing a dimensional change in the fabrication approach. This enables smaller interconnects while maintaining vertical integration benefits.
3Productivity
If TSV-based 3D ICs are used for interlayer interconnection, then vertical connectivity is improved, but die alignment precision is limited to 1 μm preventing further reduction of contact pitch
Solution Approach 1:
The patent changes the manufacturing parameters by adopting monolithic 3D fabrication processes that achieve extremely high alignment precision (around 10 nanometers), representing a ten-fold improvement over TSV-based alignment precision.
4Productivity
If TSV-based 3D ICs are used for interlayer interconnection, then vertical interconnect functionality is achieved, but TSVs are subject to intrinsic mechanical stress
Solution Approach 1:
The patent changes the physical parameters of vertical interconnects by using ILVs that are one to two orders of magnitude smaller than TSVs. This parameter change reduces the mechanical stress and susceptibility to stress-related failures while maintaining electrical connectivity.
Data Source
AI summary
Multi-layer integrated circuits having isolation cells for layer testing and related methods are disclosed. According to an aspect, an integrated circuit includes first and second layers that each have one or more electronic components. One or more electronic components of each layer can be electrically connected by a first via and a second via. The integrated circuit also includes an isolation cell operatively connected between the first via and the second via. The isolation cell is configured to controllably break electrical connection between the first via and the second via subsequent to testing of the at least one electronic component of the second layer. Example isolation cells include, but are not limited to, electronic fuses and tri-state flip-flops.