Issue Circuitry for Mixed Real-Time Execution Pipelines

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Solution Overview

Problem

Data processing systems face challenges in efficiently managing the transition between non-real time and real-time execution modes, particularly in ensuring deterministic behavior and reducing latency when switching due to the unpredictable nature of out-of-order pipelines and the need to handle pending operations.

Innovation Solution

The implementation of issue circuitry that identifies non-real time dependent registers and switches between execution modes based on trigger events, directing processing operations to either non-real time or real-time execution circuitry to maintain deterministic behavior and reduce latency by ensuring proper ordering of operations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Productivity

If out-of-order pipelines are used for non-real time execution, then throughput is improved, but latency becomes unpredictable and increases during mode transitions

Engineering Contradiction:
ImprovethroughputVSAvoidlatency
Core Design Contradiction:
ProductivityVSLoss of time

Solution Approach 1:

The execution circuitry is segmented into separate real-time and non-real-time execution pipelines. The real-time execution circuitry executes operations with deterministic latency requirements, while the non-real-time execution circuitry handles throughput-oriented operations. This segmentation allows each pipeline to be optimized for its specific performance characteristics, resolving the contradiction between throughput and latency.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

An issue policy control circuitry acts as an intermediary between the issue circuitry and the execution circuits. It receives candidate processing operations and directs them to the appropriate execution circuitry based on real-time mode status and register dependency analysis. This intermediary enables flexible routing of operations to optimize both throughput and latency performance.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of time

If mode switching is implemented to handle real-time requirements, then latency is reduced for critical operations, but system complexity increases due to mode management and register dependency tracking

Engineering Contradiction:
ImprovelatencyVSAvoidsystem complexity
Core Design Contradiction:
Loss of timeVSDevice complexity

Solution Approach 1:

The register file is divided into real-time dependent and non-real-time dependent registers, with different quality attributes assigned to each. Real-time dependent registers are those that must be accessed with deterministic timing, while non-real-time dependent registers can be accessed with relaxed timing constraints. This local differentiation allows the system to manage complexity by applying different management strategies to different registers based on their real-time requirements.

Inventive Principle:
Principle #3Local quality

Solution Approach 2:

The issue policy control circuitry changes the issue policy parameter based on the real-time mode status. When in real-time mode, it directs operations to the real-time execution circuitry with stricter timing constraints. When in non-real-time mode, it allows more flexible operation routing. This parameter change enables the system to adapt its behavior based on current workload requirements, managing complexity through dynamic configuration rather than fixed architecture.

Inventive Principle:
Principle #35Parameter changes

3Productivity

If all operations are executed in non-real time mode for maximum throughput, then productivity is improved, but real-time responsiveness deteriorates

Engineering Contradiction:
ImprovethroughputVSAvoidreal-time responsiveness
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

The execution mode is made dynamic rather than static. The issue policy control circuitry continuously monitors the real-time mode status and redirects operations accordingly. When real-time mode is active, critical operations are routed to the real-time execution circuitry to ensure responsiveness. When in normal mode, operations can be executed in the non-real-time pipeline for maximum throughput. This dynamic adaptability resolves the contradiction by allowing the system to optimize for different objectives at different times.

Inventive Principle:
Principle #15Dynamics

Solution Approach 2:

Instead of executing all operations in the non-real-time mode for maximum throughput, the system applies partial real-time execution only to operations that require it. The issue policy control circuitry identifies which operations have real-time dependencies and directs only those to the real-time execution circuitry, while leaving other operations in the non-real-time pipeline. This partial application of real-time execution maintains throughput while ensuring real-time responsiveness where needed.

Inventive Principle:
Principle #16Partial or excessive action

Data Source

PatentUS11194577B2Instruction issue according to in-order or out-of-order execution modes
Publication Date: 2021.12.07 ARM LTD
  • US11194577B2 patent drawing
  • US11194577B2 patent drawing
  • US11194577B2 patent drawing

AI summary

Apparatus for processing data (2) includes issue circuitry (22) for issuing program instructions (processing operations) to execute either within real time execution circuitry (32) or non real time execution circuitry (24, 26, 28, 30). Registers within a register file (18) are marked as non real time dependent registers if they are allocated to store a data value which is to be written by an uncompleted program instruction issued to the non real time execution circuitry and not yet completed. Issue policy control circuitry (42) responds to a trigger event to enter a real time issue policy mode to control the issue circuitry (22) to issue candidate processing operations (such as program instruction, micro-operations, architecturally triggered processing operations etc.) to one of the non real time execution circuitry or the real time execution circuitry in dependence upon whether that candidate processing operation reads a register marked as a non real time dependent register.