Iterative Bit Summation Logic for Hardware Sorting
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Solution Overview
Problem
Existing hardware solutions for sorting binary numbers suffer from significant propagation delays due to large fanout effects, leading to performance issues when sorting multiple inputs, and require large hardware arrangements to mitigate these delays.
Innovation Solution
A method and hardware logic unit that iteratively select the ith largest or pth smallest number from a set of n m-bit numbers by summing bits, comparing the summation result to a threshold, and updating bits based on the comparison outcome, reducing the need for initial sorting and minimizing hardware size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional sorting hardware with multiple logic blocks is used, then sorting capability is achieved, but propagation delay increases due to large fanout effects
Solution Approach 1:
The patent segments the sorting function into multiple independent processing stages, where each stage handles a specific bit position or comparison task. This segmentation reduces the fanout at any single logic block, as each segment processes only a portion of the overall sorting task, thereby reducing propagation delay while maintaining complete sorting capability through the combination of all segments.
2Speed
If buffers are added to reduce propagation delay, then sorting speed improves, but hardware area increases significantly
Solution Approach 1:
The patent extracts and eliminates the need for large numbers of buffers by redesigning the logic block architecture. Instead of using buffers to mitigate fanout effects, the invention restructures the logic blocks to inherently limit fanout through functional decomposition, achieving high sorting speed without the hardware area penalty of adding numerous buffers.
3Reliability
If conventional sorting hardware is used, then numbers can be sorted, but hardware size becomes large to mitigate delay
Solution Approach 1:
The patent merges multiple functions into a single optimized logic block design that performs comparison, selection, and bit manipulation operations simultaneously. This consolidation eliminates the need for separate sorting networks and associated hardware, achieving complete sorting functionality in a compact configuration that reduces overall hardware size while maintaining reliable sorting performance.
Data Source
AI summary
A method of selecting, in hardware logic, an ith largest or a pth smallest number from a set of n m-bit numbers is described. The method is performed iteratively and in the rth iteration, the method comprises: summing an (m−r)th bit from each of the m-bit numbers to generate a summation result and comparing the summation result to a threshold value. Depending upon the outcome of the comparison, the rth bit of the selected number is determined and output and additionally the (m−r−1)th bit of each of the m-bit numbers is selectively updated based on the outcome of the comparison and the value of the (m−r)th bit in the m-bit number. In a first iteration, a most significant bit from each of the m-bit numbers is summed and each subsequent iteration sums bits occupying successive bit positions in their respective numbers.